TMS570LS1114 datasheet(54/169 Pages) TI1

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TMS570LS1114

SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015

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6.4

Warm Reset (nRST)

This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset

condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the

output buffer is implemented as an open drain (drives low only). To ensure an external reset is not

arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.

This terminal has a glitch filter. It also has an internal pullup.

6.4.1

Causes of Warm Reset

Table 6-5. Causes of Warm Reset

DEVICE EVENT

SYSTEM STATUS FLAG

Power-Up Reset

Exception Status Register, bit 15

Oscillator fail

Global Status Register, bit 0

PLL slip

Global Status Register, bits 8 and 9

Watchdog exception / Debugger reset

Exception Status Register, bit 13

Software Reset

Exception Status Register, bit 4

External Reset

Exception Status Register, bit 3

6.4.2

nRST Timing Requirements

Table 6-6. nRST Timing Requirements

PARAMETER

MIN

MAX

UNIT

tv(RST)

Valid time, nRST active after

2256 tc(OSC)

(1)

nPORRST inactive

Valid time, nRST active (all other

32 tc(VCLK)

System reset conditions)

tf(nRST)

475

2000

Filter time nRST pin;

pulses less than MIN will be

filtered out, pulses greater than

MAX will generate a reset

(1)

Assumes the oscillator has started up and stabilized before nPORRST is released ..

System Information and Electrical Specifications

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