MCP2050 datasheet(4/40 Pages) MICROCHIP

4 / 40 page

MCP2050

DS20002299C-page 4

 2012-2014 Microchip Technology Inc.

1.1.1

POWER-ON-RESET MODE

Upon application of VBB, or whenever the voltage on

VBB is below the threshold of regulator turn-off voltage

VOFF (typically. 4.50V), the device enters Power-On

Reset mode (POR). During this mode, the device

maintains the digital section in a reset mode and waits

until the voltage on pin VBB rises above the threshold of

regulator turn-on voltage VON (typically 5.75V) to enter

into Ready mode. In Power-On-Reset mode, the LIN

physical layer and voltage regulator are disabled, and

RESET output is forced to low.

1.1.2

READY MODE

The device enters Ready mode from POR mode after

the voltage on VBB rises above the threshold of

regulator turn-on voltage VON or from Power-Down

mode when a remote or local wake-up event happens.

Upon entering Ready mode, the voltage regulator and

receiver section of the transceiver are powered up. The

transmitter remains in off state. The device is ready to

receive data but not to transmit. In order to minimize the

power consumption, the regulator operates in a

reduced-power mode. It has a lower GBW product and

thus is slower. However, the 70 mA drive capability is

unchanged.

The device stays in Ready mode until the output of the

voltage regulator has stabilized and the CS/LWAKE pin

is high (‘1’).

1.1.3

OPERATION MODE

If VREG is OK (VREG > 0.8 VREG_NOM), CS/LWAKE

pin, FAULT/TXE pin and TXD pin are high, the part

enters the Operation mode from either Ready or

Transmitter Off mode.

In this mode, all internal modules are operational. The

internal pull-up resistor between LBUS and VBB is

connected only in this mode.

The device goes into the Power-Down mode at the fall-

ing edge on CS/LWAKE; or to the Transmitter Off mode

at the falling on FAULT/TXE while CS/LWAKE stays high.

1.1.4

TRANSMITTER OFF MODE

In Transmitter Off mode, the receiver is enabled but the

LBUS transmitter is off. It is a lower-power mode.

In order to minimize the power consumption, the

window watchdog timer is disabled and the regulator

operates in a reduced-power mode. It has a lower

GBW product and thus is slower. However, the 70 mA

drive capability is unchanged.

The transmitter may be re-enabled whenever the

FAULT/TXE signal returns high, by removing the

internal fault condition and the CPU returning the

FAULT/TXE high. The transmitter will not be enabled

even if the FAULT/TXE pin is brought high externally,

when the internal fault is still present. However,

externally forcing the FAULT/TXE high, while the

internal fault is still present, should be avoided since

this will induce high current and power dissipation in

the FAULT/TXE pin.

The transmitter is also turned off whenever the voltage

regulator is unstable or recovering from a fault. This

prevents unwanted disruption of the bus during times of

uncertain operation.

1.1.5

POWER-DOWN MODE

In Power-Down mode, the transceiver and the voltage

regulator are both off. Only the Bus Wake-up section

and the CS/LWAKE pin wake-up circuits are in opera-

tion. This is the lowest-power mode.

If any bus activity (e.g. a BREAK character) occurs

during Power-Down mode, the device will immediately

enter Ready mode and enable the voltage regulator.

Then, once the regulator output has stabilized (approx-

imately 0.3 ms to 1.2 ms) it goes to Operation mode.

Refer to Section 1.1.6 “Remote Wake-up” for more

details.

The part will also enter Ready mode from Power-Down

mode, followed by Operation mode, if the CS/LWAKE

pin becomes active high (‘1’).

1.1.6

REMOTE WAKE-UP

The remote wake-up sub module observes the LBUS in

order to detect bus activity. In Power-Down mode, nor-

mal LIN recessive/dominant threshold is disabled, and

the LIN bus Wake-Up Voltage Threshold VWK(LBUS) is

used to detect bus activities. Bus activity is detected

when the voltage on the LBUS falls below the LIN bus

Wake-Up Voltage Threshold VWK(LBUS) (approximately

3.4V) for at least tBDB (a typical duration of 80 µs) fol-

lowed by a rising edge. Such a condition causes the

device to leave Power-Down mode

MCP2050 Datasheet(PDF) 4 Page - Microchip Technology

MCP2050 Datasheet(HTML) 4 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL