MCP2050 datasheet(9/40 Pages) MICROCHIP

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 2012-2014 Microchip Technology Inc.

DS20002299C-page 9

MCP2050

1.3.4

VREG

Positive Supply Voltage Regulator Output pin. An on-

chip LDO gives +5.0 or +3.3V 70 mA regulated voltage

on this pin.

1.3.5

TXD

Transmit Data Input pin (TTL level, HV compliant,

adaptive pull-up). The transmitter reads the data

stream on TXD pin and sends it to LIN bus. The LBUS

pin is low (dominant) when TXD is low, and high

(recessive) when TXD is high.

The Transmit Data Input pin has an internal adaptive

pull-up to an internally-generated 4.2V (approximate).

When TXD is ‘0’, a weak pull-up (~900 kΩ) is used to

reduce current. When TXD is ‘1’ a stronger pull-up

(~300 kΩ) is used to maintain the logic level. A series

reverse-blocking diode allows applying TXD input

voltages greater than the internally generated 4.2V and

renders TXD pin HV compliant up to 30V (see the Block

Diagram on page 2).

1.3.6

RESET

Reset Output pin. This pin is open drain with ~90 kΩ

pull-up to VREG. It indicates the internal voltage has

reached a valid, stable level. As long as the internal

voltage is valid (above 0.8VREG), this pin will remain

high (‘1’); otherwise the RESET pin switches to low (‘0’).

1.3.7

VSS

Ground pin.

1.3.8

LBUS

LBUS is a bidirectional LIN bus Interface pin and is

controlled by the signal TXD. It has an open collector

output

with

current

limitation.

reduce

electromagnetic emission, the slopes during signal

changes are controlled, and the LBUS pin has

corner-rounding control for both falling and rising edges.

The internal LIN receiver observes the activities on LIN

bus, and generates the output signal RXD that follows

the state of the LBUS. A first degree 160 kHz, low-pass

input filter optimizes electromagnetic immunity.

1.3.9

VBB

Battery Positive Supply Voltage pin. An external diode

is connected in series to prevent the device from being

reversely powered (refer Figure 1-12).

1.3.10

FAULT/TXE

Fault Detect Output/Transmitter Enable Input pin. The

output section is HV tolerant open drain (up to 30V).

The input section is identical with TXD section (TTL

level, HV compliant, adaptive pull-up). The internal pull-

up resistor may be too weak for some applications. An

external 10kΩ pull-up resistor is recommended to

ensure a logic high level. Its state is defined as shown

in Table 1-3. The device is placed in Transmitter Off

mode whenever this pin is low (‘0’), either from an

internal fault condition or by external drive.

If CS/LWAKE is high (‘1’), the FAULT/TXE signals a mis-

match between the TXD input and the LBUS level. This

can be used to detect a bus contention. Since the bus

exhibits a propagation delay, the sampling of the inter-

nal compare is debounced to eliminate false faults.

After the device wakes up, the FAULT/TXE indicates

what wakes the device if CS/LWAKE remains low (‘0’)

(refer to Table 1-3).

The FAULT/TXE pin sampled at a rate faster than every

10 µs.

1.3.11

WWDTSELECT

This is an analog input pin that sets the open window

time to accept a trigger reset. A resistor between this

pin and VSS sets this time. The equation to determine

the value of the resistor can be found in Section 1.2.2

“Windowed Watchdog Behavior”

1.3.12

WWDTTRIG

This is an input pin to reset the Windowed Watchdog

Timer. A high-to-low transition during the open window

time will reset the timer and prevent the WWDT from

timing out. The pin has an internal adaptive pull-up to

an internally-generated 4.2V (approximate.).

When WWDTTRIG is ‘0’, a weak pull-up (~800 kΩ

is

connected

to reduce current.

When WWDTTRIG is ‘1’, the pull-up is stronger to

maintain the logic level.

1.3.13

WWDTRESET

WWDTRESET is an open-drain output pin. This pin is

asserted low when the internal Windowed Watchdog

Timer has expired or an attempt was made to clear the

timer before the window has opened.

1.3.14

It is recommended to connect this pad to VSS to enhance

electromagnetic immunity and thermal resistance.

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