ADS8345EB datasheet(15/18 Pages) TI

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ADS8345

SBAS177C

www.ti.com

POWER DISSIPATION

There are three power modes for the ADS8345: full-power

(PD1-PD0 = 11B), auto power-down (PD1-PD0 = 00B), and

shutdown (SHDN LOW). The effects of these modes varies

depending on how the ADS8345 is being operated. For

example, at full conversion rate and 24-clocks per conver-

sion,

there

very

little

difference

between

full-power mode and auto power-down; a shutdown will not

lower power dissipation.

When operating at full-speed and 24-clocks per conversion

(see Figure 6), the ADS8345 spends most of its time acquir-

ing or converting. There is little time for auto power-down,

assuming that this mode is active. Thus, the difference

between full-power mode and auto power-down is negligible.

If the conversion rate is decreased by simply slowing the

frequency of the DCLK input, the two modes remain approxi-

mately equal. However, if the DCLK frequency is kept at the

maximum rate during a conversion, but conversions are

simply done less often, then the difference between the two

modes is dramatic. In the latter case, the converter spends

an increasing percentage of its time in power-down mode

(assuming the auto power-down mode is active).

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tACQ

Acquisition Time

1.7

µs

tDS

DIN Valid Prior to DCLK Rising

tDH

DIN Hold After DCLK HIGH

tDO

DCLK Falling to DOUT Valid

100

tDV

CS Falling to DOUT Enabled

tTR

CS Rising to DOUT Disabled

tCSS

CS Falling to First DCLK Rising

tCSH

CS Rising to DCLK Ignored

tCH

DCLK HIGH

150

tCL

DCLK LOW

150

tBD

DCLK Falling to BUSY Rising

100

tBDV

CS Falling to BUSY Enabled

tBTR

CS Rising to BUSY Disabled

TABLE VII. Timing Specifications (+VCC = +4.75V to +5.25V,

TA = –40°C to +85°C, and CLOAD = 50pF).

Data Format

The output data from the ADS8345 is in Binary Two’s

Complement format, as shown in Table VIII. This table

represents the ideal output code for the given input voltage

and does not include the effects of offset, gain error, or noise.

If DCLK is active and CS is LOW while the ADS8345 is in

auto power-down mode, the device will continue to dissipate

some power in the digital logic. The power can be reduced

to a minimum by keeping CS HIGH.

Operating the ADS8345 in auto power-down mode will result

in the lowest power dissipation, and there is no conversion

time “penalty” on power-up. The very first conversion will be

valid. SHDN can be used to force an immediate power-down.

NOISE

The noise floor of the ADS8345 itself is rather low (see

Figures 10 and 11). The ADS8345 was tested at both 5V and

2.7V, and in both the internal and external clock modes. A

low-level DC input was applied to the analog-input pins and

the converter was put through 5000 conversions. The digital

output of the A/D converter will vary in output code due to the

internal noise of the ADS8345. This is true for all 16-bit, SAR-

type, A/D converters. Using a histogram to plot the output

codes, the distribution should appear bell-shaped with the

peak of the bell curve representing the nominal code for the

input value. The

±1σ, ±2σ, and ±3σ distributions will repre-

sent the 68.3%, 95.5%, and 99.7%, respectively, of all codes.

The transition noise can be calculated by dividing the number

of codes measured by 6 and this will yield the

±3σ distribu-

tion, or 99.7%, of all codes. Statistically, up to 3 codes could

fall outside the distribution when executing 1000 conver-

sions. The ADS8345, with 5 output codes for the

±3σ

distribution, will yield a <

±0.83LSB transition noise at 5V

operation. Remember, to achieve this low-noise performance,

the peak-to-peak noise of the input signal and reference

must be < 50

µV.

DESCRIPTION

ANALOG VALUE

Full-Scale Range

2 • VREF

Least Significant

2 • VREF/65536

Bit (LSB)

BINARY CODE

HEX CODE

+Full-Scale

+VREF – 1LSB

0111 1111 1111 1111

7FFF

Midscale

0000 0000 0000 0000

0000

Midscale – 1LSB

0V – 1LSB

1111 1111 1111 1111

FFFF

–Full-Scale

–VREF

1000 0000 0000 0000

8000

DIGITAL OUTPUT

BINARY TWO’S COMPLEMENT

TABLE VIII. Ideal Input Voltages and Output Codes.

FIGURE 10. Histogram of 5000 Conversions of a DC Input at

the Code Transition, 5V operation external clock

mode. VREF = VCOM = 2.5V.

FFFEH

FFFFH

Code

0000H

0001H

0002H

701

122

3544

568

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