ADS8345EB datasheet(16/18 Pages) TI

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ADS8345

SBAS177C

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FIGURE 11. Histogram of 5000 Conversions of a DC Input at

the Code Center, 2.7V operation external clock

mode. VREF = VCOM = 1.25V.

output of the analog comparator. Thus, during any single

conversion for an n-bit SAR converter, there are n “windows”

in which large external transient voltages can easily affect

the conversion result. Such glitches might originate from

switching power supplies, nearby digital logic, and high-

power devices. The degree of error in the digital output

depends on the reference voltage, layout, and the exact

timing of the external event. The error can change if the

external event changes in time with respect to the DCLK

input.

With this in mind, power to the ADS8345 should be clean and

well bypassed. A 0.1

µF ceramic bypass capacitor should be

placed as close to the device as possible. In addition, a 1

µF

to 10

µF capacitor and a 5Ω or 10Ω series resistor may be

used to low-pass filter a noisy supply.

The reference should be similarly bypassed with a 0.1

µF

capacitor. Again, a series resistor and large capacitor can be

used to low-pass filter the reference voltage. If the reference

voltage originates from an op amp, make sure that it can

drive the bypass capacitor without oscillation (the series

resistor can help in this case). The ADS8345 draws very little

current from the reference on average, but it does place

larger demands on the reference circuitry over short periods

of time (on each rising edge of DCLK during a conversion).

The ADS8345 architecture offers no inherent rejection of

noise or voltage variation in regards to the reference input.

This is of particular concern when the reference input is tied

to the power supply. Any noise and ripple from the supply will

appear directly in the digital results. While high-frequency

noise can be filtered out as discussed in the previous

paragraph, voltage variation due to line frequency (50Hz or

60Hz) can be difficult to remove.

The GND pin should be connected to a clean ground point.

In many cases, this will be the “analog” ground. Avoid

connections which are too near the grounding point of a

microcontroller or digital signal processor. If needed, run a

ground trace directly from the converter to the power-supply

entry point. The ideal layout will include an analog ground

plane dedicated to the converter and associated analog

circuitry.

AVERAGING

The noise of the A/D converter can be compensated by

averaging the digital codes. By averaging conversion results,

transition noise will be reduced by a factor of 1/

√n, where n

is the number of averages. For example, averaging 4 conver-

sion results will reduce the transition noise by 1/2 to

±0.25LSBs. Averaging should only be used for input signals

with frequencies near DC.

For AC signals, a digital filter can be used to low-pass filter

and decimate the output codes. This works in a similar

manner to averaging: for every decimation by 2, the

signal-to-noise ratio will improve 3dB.

LAYOUT

For optimum performance, care should be taken with the

physical layout of the ADS8345 circuitry. This is particularly

true if the reference voltage is LOW and/or the conversion

rate is HIGH.

The basic SAR architecture is sensitive to glitches or sudden

changes on the power supply, reference, ground connec-

tions, and digital inputs that occur just prior to latching the

436

780

2305

938

435

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Code

0000H

0001H

0002H

0003H

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