A29400B datasheet(6/34 Pages) AMICC

6 / 34 page

A29400B Series

PRELIMINARY

(June, 2016, Version 0.0)

AMIC Technology, Corp.

Word/Byte Configuration

The

BYTE pin determines whether the I/O pins I/O15-I/O0

operate in the byte or word configuration. If the

BYTE pin is

set at logic ”1”, the device is in word configuration, I/O15-I/O0

are active and controlled by

CE and OE .

If the

BYTE pin is set at logic “0”, the device is in byte

configuration, and only I/O0-I/O7 are active and controlled by

CE and OE . I/O8-I/O14 are tri-stated, and I/O15 pin is used

as an input for the LSB(A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive

the

CE and OE pins to VIL. CE is the power control and

selects the device.

OE is the output control and gates array

data to the output pins.

WE should remain at VIH all the

time during read operation. The internal state machine is set

for reading array data upon device power-up, or after a

hardware reset. This ensures that no spurious alteration of

the memory content occurs during the power transition. No

command is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid data

on the device data outputs. The device remains enabled for

read access until the command register contents are

altered.

See "Reading Array Data" for more information. Refer to the

AC Read Operations table for timing specifications and to

the Read Operations Timings diagram for the timing

waveforms, lCC1 in the DC Characteristics table represents

the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes

programming data to the device and erasing sectors of

memory), the system must drive

WE and CE to VIL, and

OE to VIH. An erase operation can erase one sector,

multiple sectors, or the entire device. The Sector Address

Tables indicate the address range that each sector

occupies. A "sector address" consists of the address inputs

required to uniquely select a sector. See the "Command

Definitions" section for details on erasing a sector or the

entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence,

the device enters the autoselect mode. The system can

then read autoselect codes from the internal register (which

is separate from the memory array) on I/O7 - I/O0. Standard

read cycle timings apply in this mode. Refer to the

"Autoselect Mode" and "Autoselect Command Sequence"

sections for more information.

ICC2 in the DC Characteristics table represents the active

current

specification

for

the

write

mode.

The

"AC

Characteristics" section contains timing specification tables

and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status bits

on I/O7 - I/O0. Standard read cycle timings and ICC read

specifications apply. Refer to "Write Operation Status" for

more information, and to each AC Characteristics section

for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it

can place the device in the standby mode. In this mode,

current consumption is greatly reduced, and the outputs are

placed in the high impedance state, independent of the

input.

The device enters the CMOS standby mode when the

& RESET pins are both held at VCC ± 0.5V. (Note that this

is a more restricted voltage range than VIH.) The device

enters the TTL standby mode when

CE is held at VIH, while

RESET is held at VCC±0.5V. The device requires the

standard access time (tCE) before it is ready to read data.

If the device is deselected during erasure or programming,

the device draws active current until the operation is

completed.

ICC3 in the DC Characteristics tables represents the standby

current specification.

Output Disable Mode

When the

OE input is at VIH, output from the device is

disabled. The output pins are placed in the high impedance

state.

RESET : Hardware Reset Pin

The RESET pin provides a hardware method of resetting

the device to reading array data. When the system drives

the RESET pin low for at least a period of tRP, the device

immediately terminates any operation in progress, tristates

all data output pins, and ignores all read/write attempts for

the duration of the RESET pulse. The device also resets

the internal state machine to reading array data. The

operation that was interrupted should be reinitiated once the

device is ready to accept another command sequence, to

ensure data integrity.

The RESET pin may be tied to the system reset circuitry. A

system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from the

Flash memory.

Refer

the

Characteristics

tables

for RESET

parameters and diagram.

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