®

OPA121

6

–10

–5

0

+5

+10

–20

–10

0

10

20

30

40

50

60

70

80

LF155

OP-15/16/17 "Perfect Bias Current Cancellation"

AD547

OPA121

LF156/157

AD547

LF155

OPA121

LF156/157

A

T = +25°C; curves taken from

mfg. published typical data

Common-Mode Voltage (VDC)

this may cause a noticeable degradation of offset voltage and

drift.

Static protection is recommended when handling any

precision IC operational amplifier.

GUARDING AND SHIELDING

As in any situation where high impedances are involved,

careful shielding is required to reduce “hum” pickup in input

leads. If large feedback resistors are used, they should also

be shielded along with the external input circuitry.

Leakage currents across printed circuit boards can easily

exceed the bias current of the OPA121. To avoid leakage

problems, it is recommended that the signal input lead of the

OPA121 be wired to a Teflon™ standoff. If the OPA121 is

to be soldered directly into a printed circuit board, utmost

care must be used in planning the board layout. A “guard”

pattern should completely surround the high-impedance in-

put leads and should be connected to a low-impedance point

which is at the signal input potential.

The amplifier case should be connected to any input shield

or guard via pin 8. This insures that the amplifier itself is

fully surrounded by guard potential, minimizing both leak-

age and noise pickup (see Figure #2).

If guarding is not required, pin 8 (case) should be connected

to ground.

BIAS CURRENT CHANGE

VERSUS COMMON-MODE VOLTAGE

The input bias currents of most popular BIFET operational

amplifiers are affected by common-mode voltage (Figure 3).

Higher input FET gate-to-drain voltage causes leakage and

ionization (bias) currents to increase. Due to its cascode

input stage, the extremely-low bias current of the OPA121

is not compromised by common-mode voltage.

FIGURE 2. Connection of Input Guard.

7

6

8

TO-99 Bottom View

3

OPA121

2

8

6

In

Out

Non-Inverting

3

OPA121

2

8

6

In

Out

Buffer

3

OPA121

2

8

6

In

Out

Inverting

3

2

4 5

6

7

8

1

Mini-DIP Bottom View

3

2

4

1

5

BOARD LAYOUT

FOR INPUT GUARDING

Guard top and bottom of board.

Alternate: use Teflon standoff

for sensitive input pins.

FIGURE 3. Input Bias Current vs Common-Mode Voltage.

Teflon™ E.I. du Pont de Nemours & Co.