11

®

OPA655

differential gain of 1.5V/V (3.5dB) to the matched load as

shown in Figure 10. The C

match the high frequency gains for the two signal paths to

improve the high frequency CMRR. Using this adjustment,

a CMRR > 40dB through 100MHz was achieved.

HIGH SPEED INSTRUMENTATION

DIFFERENTIAL AMPLIFIER

Very high speed differential amplifiers can be implemented

using the OPA655. The very low input bias currents allow

relatively high resistor values to be used in a standard single

op amp differential configuration. Alternatively, a very high

input impedance differential amplifier can be implemented

using a three op amp instrumentation amplifier topology as

shown in Figure 9.

FIGURE 8. Maximally Flat Bandwidth.

FIGURE 9. High Input Impedance, Broadband INA.

50

Ω

Load

50

Ω

OPA651

R

G

100

Ω

R

F

100

Ω

300

Ω

300

Ω

R

F

100

Ω

OPA655

OPA655

300

Ω

C

T

1.5 to 6pF

300

Ω

In this example, the OPA655’s provide a differential gain of:

and a common mode gain of 1 to the input of the OPA651

differential stage. The OPA651, a gain of 2 stable, broad-

band voltage feedback op amp, rejects the common mode

signal and provides a differential gain of 1/2 the matched

50

Ω load. This circuit delivers a 136MHz bandwidth at a

1

+

2R

F

R

G









= 3

FIGURE 10. Measured Frequency Response for INA.

DIFFERENTIAL INPUT

3.5dB

2.5

1.5

.5

1M

10M

100M

1G

136MHz

OPTIMIZING PERFORMANCE

DC ACCURACY

The OPA655 is laser trimmed for low input offset voltage,

limiting the need for external trim circuits. In most cases, the

low bias current of the FET input will not contribute signifi-

cantly to the output DC error. For example, at minimum gain

(G = +1) and maximum temperature (85

°C), the error

contribution due to the inverting input bias current would

only exceed the input offset voltage for feedback resistors >

(1mV/3.2nA) = 312k

Ω. Only for relatively high source and/

or feedback resistor values will the input bias current con-

tribute significantly to the output DC error. Similarly, since

the two input bias currents are very low, but not tightly

matched, input bias current cancellation through source

impedance matching is not recommended.

Changes in the power supply voltages contribute to shifts

in the input offset voltage. This can be calculated using

the PSR specifications. For example, a 0.5V change in

the negative power supply will show up typically as a

Negative common mode voltage inputs can cause an in-

crease in the input bias currents as shown in the Typical

Performance Curves. This can have an effect on DC accu-

racy when the source and/or feedback resistors are large and

the common mode input voltage approaches the negative

limit of –2.5V. Positive input biases are therefore preferred

for diode transimpedance applications requiring a bias volt-

age on the non-inverting op amp input.

BANDWIDTH vs R

F

10

30

10

0.3

1

Transimpedance Gain, R

100

1000

C

C

C

C

C