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DS90C387 Datasheet(PDF) 19 Page - National Semiconductor (TI) |
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DS90C387 Datasheet(HTML) 19 Page - National Semiconductor (TI) |
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19 / 26 page ![]() LVDS Interface (Continued) 10007304 Note that the LVDS Clock signal is also DC Balanced in this mode. The rising edge location is fixed, but the location of the falling edge will be in one of two locations as shown above. Optional features supported: Pre-emphasis, and Deskew. FIGURE 18. 48 Parallel TTL Data Inputs Mapped to LVDS Outputs DC Balanced Mode - Data Enabled, BAL=High www.national.com 19 |
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