GS4915 ClockCleaner™

Data Sheet

39145 - 5

June 2009

13 of 27

3.2.1 Differential Clock Input

A differential LVDS clock signal conforming to the TIA/EIA-644-A standard may be

AC-coupled to the CLKIN and CLKIN pins.

If the GS4911B/10B/01B/00B is used, the PCLK3 and PCLK3 outputs from that device

may be directly connected to the CLKIN and CLKIN inputs of the GS4915, respectively.

The CLKIN and CLKIN input traces should be tightly-coupled with a controlled

differential impedance of 100Ω. The pair should be terminated with 100Ω at the input

to the device as no internal termination is provided.

This input clock is selected as the one to be cleaned by the GS4915 when the IPSEL pin

is set LOW.

The clock can be DC coupled if the levels are appropriate, but only AC coupling is

recommended. These inputs are both LVDS and CML compatible, and AC coupling is

only required in cases where the common mode does not line up.

3.2.2 Single-Ended Clock Input

A single-ended clock signal at from 1.8V - 3.3V CMOS levels may be DC-coupled to the

CLKIN_SE pin.

If the GS4911B/10B/01B/00B is used, the PCLK1 or PCLK2 output from that device may

be directly connected to the CLKIN_SE input of the GS4915.

3.2.3 Input Clock Selection

An internal 2x1 input multiplexer is provided to allow switching between the

differential and single-ended clock inputs using one external pin. When IPSEL is set

LOW, the differential clock at the CLKIN/CLKIN pins is selected as the one to be

processed by the device. When IPSEL is set HIGH, the single-ended clock at the

CLKIN_SE pin is selected as the one to be processed.

3.2.4 Unused Clock Inputs

If the application will only provide a differential clock input, then the CLKIN_SE input

pin should be connected to AGND.

If only a single-ended clock will be provided, then the CLKIN/CLKIN pins should be left

unconnected.

3.3 Clock Cleaning PLL

To obtain a low-jitter output clock signal, the GS4915 uses a clock cleaning phase-locked

loop. This block will always attempt to lock an external 1.485GHz VCO signal to the

selected input clock. Internal dividers, set by the digital control block based on the

frequency mode of the device (see Section 3.4.1), are used to obtain the final output