GS4915 ClockCleaner™

Data Sheet

39145 - 5

June 2009

21 of 27

Figure 3-2: Output skew behaviour of GS4915

3.7 Clock Outputs

The GS4915 presents both differential and single-ended clock outputs. When the LOCK

output signal is HIGH, these clock outputs will be low-jitter and locked to the selected

input clock.

NOTE: If in Manual Bypass mode, the LOCK pin may be HIGH although the output clock

will always be a copy of the input clock, and NOT the cleaned clock.

The frequency of the differential and single-ended clock outputs will be identical and

will be determined as described in Section 3.5.

3.7.1 Differential Clock Output

A CML-based driver is used to provide the differential clock output at the CLKOUT and

CLKOUT pins. Although this driver will output a signal amplitude that is compatible to

the TIA/EIA-644 LVDS standard, it has an incompatible common mode level. Therefore,

AC-coupling and external biasing resistors are required if interfacing the differential

clock outputs from the GS4915 to a true LVDS receiver. The common mode is, however,

compatible with the LVDS inputs on most FPGAs and can be DC coupled.

This is the lowest-jitter output of the GS4915.

The differential clock output driver uses a separate power supply of +1.8V DC supplied

via the DIFF_OUT_VDD pin.

3.7.2 Single-Ended Clock Output

The single-ended output clock is present at the CLKOUT_SE pin. The signal will operate

at either 1.8V or 3.3V CMOS levels, as determined by the voltage applied to the SE_VDD

pin.

The single-ended clock output pre-drive uses a separate power supply of +1.8V DC

supplied via the D_VDD pin.

3.8 Device Reset

3.8.1 Hardware Reset

In order to reset the GS4915 to their defaults conditions, the RESET pin must be held

Device Latency

1/4 CLK Period - Device Latency

Input Clock

Output Clock

SKEW_EN = LOW

SKEW_EN = HIGH