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DS90CF562 Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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DS90CF562 Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 12 page  Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Units TRANSMITTER SUPPLY CURRENT I CCTZ Transmitter Supply Current, Power Down Power Down = Low 125 µA RECEIVER SUPPLY CURRENT I CCRW Receiver Supply Current, Worst Case C L = 8 pF, Worst Case Pattern ( Figure 1, Figure 4) f = 32.5 MHz 55 75 mA f = 37.5 MHz 60 80 mA I CCRG Receiver Supply Current, 16 Grayscale C L = 8 pF, 16 Grayscale Pattern ( Figure 2, Figure 4) f = 32.5 MHz 35 55 mA f = 37.5 MHz 37 58 mA I CCRZ Receiver Supply Current, Power Down Power Down = Low 110 µA Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Note 2: Typical values are given for VCC = 5.0V and TA = +25˚C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci- fied (except VOD and ∆VOD). Note 4: ESD Rating: HBM (1.5 k Ω, 100 pF) PLL V CC ≥ 1000V All other pins ≥ 2000V EIAJ (0 Ω, 200 pF) ≥ 150V Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units LLHT LVDS Low-to-High Transition Time ( Figure 3) 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time ( Figure 3) 0.75 1.5 ns TCIT TxCLK IN Transition Time ( Figure 5)8 ns TCCS TxOUT Channel-to-Channel Skew (Note 5) ( Figure 6) 350 ps TPPos0 Transmitter Output Pulse Position for Bit 0 ( Figure 17)f = 20 MHz −200 150 350 ps TPPos1 Transmitter Output Pulse Position for Bit 1 6.3 7.2 7.5 ns TPPos2 Transmitter Output Pulse Position for Bit 2 12.8 13.6 14.6 ns TPPos3 Transmitter Output Pulse Position for Bit 3 20 20.8 21.5 ns TPPos4 Transmitter Output Pulse Position for Bit 4 27.2 28 28.5 ns TPPos5 Transmitter Output Pulse Position for Bit 5 34.5 35.2 35.6 ns TPPos6 Transmitter Output Pulse Position for Bit 6 42.2 42.6 42.9 ns TPPos0 Transmitter Output Pulse Position for Bit 0 ( Figure 16)f = 40 MHz −100 100 300 ps TPPos1 Transmitter Output Pulse Position for Bit 1 2.9 3.3 3.9 ns TPPos2 Transmitter Output Pulse Position for Bit 2 6.1 6.6 7.1 ns TPPos3 Transmitter Output Pulse Position for Bit 3 9.7 10.2 10.7 ns TPPos4 Transmitter Output Pulse Position for Bit 4 13 13.5 14.1 ns TPPos5 Transmitter Output Pulse Position for Bit 5 17 17.4 17.8 ns TPPos6 Transmitter Output Pulse Position for Bit 6 20.3 20.8 21.4 ns TCIP TxCLK IN Period ( Figure 7) 25 T 50 ns TCIH TxCLK IN High Time ( Figure 7) 0.35T 0.5T 0.65T ns TCIL TxCLK IN Low Time ( Figure 7) 0.35T 0.5T 0.65T ns TSTC TxIN Setup to TxCLK IN ( Figure 7)f = 20 MHz 14 ns f = 40 MHz 8 ns THTC TxIN Hold to TxCLK IN ( Figure 7) 2.5 2 ns www.national.com 4 |
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