Over recommended operating supply and temperature ranges unless otherwise specified

Symbol

Parameter

Min

Typ

Max

Units

TCCD

5

9.7

ns

V

TPLLS

Transmitter Phase Lock Loop Set (

Figure 11)10

ms

TPDD

Transmitter Powerdown Delay (

Figure 15)

100

ns

Note 5: This limit based on bench characterization.

Receiver Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol

Parameter

Min

Typ

Max

Units

CLHT

CMOS/TTL Low-to-High Transition Time (

Figure 4)

3.5

6.5

ns

CHLT

CMOS/TTL High-to-Low Transition Time (

Figure 4)

2.7

6.5

ns

RCOP

RxCLK OUT Period (

Figure 8)

25

T

50

ns

RSKM

Receiver Skew Margin (Note 6). V

1.1

ns

f = 40 MHz

700

ps

RCOH

RxCLK OUT High Time (

Figure 8)f = 20 MHz

21.5

ns

f = 40 MHz

10.5

ns

RCOL

RxCLK OUT Low Time (

Figure 8)f = 20 MHz

19

ns

f = 40 MHz

6

ns

RSRC

RxOUT Setup to RxCLK OUT (

Figure 8)f = 20 MHz

14

ns

f = 40 MHz

4.5

ns

RHRC

RxOUT Hold to RxCLK OUT (

Figure 8)f = 20 MHz

16

ns

f = 40 MHz

6.5

ns

RCCD

7.6

11.9

ns

V

RPLLS

Receiver Phase Lock Loop Set (

Figure 12)10

ms

RPDD

Receiver Powerdown Delay (

Figure 16)1

µs

Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew(TCCS)

and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on type/length and source clock(TxCLK IN) jitter.

RSKM

≥ cable skew (type, length) + source clock jitter (cycle to cycle)

AC Timing Diagrams

DS012485-5

FIGURE 1. “Worst Case” Test Pattern

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