VIN

GND

VOUT

PG

VOS

AVIN

EN

SS/TR

AGND

FB

MODE

C1

C3

R4

C2

L1

R2

R1

Single Point

Ground

TPS62097

www.ti.com

SLVSCD6 – DECEMBER 2015

11 PCB Layout

11.1 Layout Guidelines

•

TI recommends to place all components as close as possible to the IC. Specially, the input capacitor

placement must be closest to the PVIN and PGND pins of the device.

•

The low side of the input and output capacitors must be connected directly to the PGND pin to avoid a ground

potential shift.

•

Use the input capacitor's terminals as the common node for AVIN and PVIN, AGND and PGND. It helps to

reduce the noise coupling into the internal analog circuit blocks. Don't use a solid plane pour to connect these

nodes.

•

Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance.

•

The sense trace connected to VOS pin is a signal trace. Special care should be taken to avoid noise being

induced. By a direct routing, parasitic inductance can be kept small. Keep the trace away from SW nodes.

•

Refer to Figure 32 for an example of component placement, routing and thermal design.

11.2 Layout Example

Figure 32. TPS62097 PCB Layout

11.3 Thermal Information

Implementation of integrated circuits in low-profile and fine pitch surface mount packages typically requires

special attention to power dissipation. Many system dependent issues such as thermal coupling, airflow, added

heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-

dissipation limits of a given component.

Thermal Information provides the thermal metric of the device on the TPS62097 EVM after considering the PCB

design of real applications. The big copper planes connecting to the pads of the IC on the PCB board improve

the thermal performance of the device. For more details on how to use the thermal parameters, see the

application notes: Thermal Characteristics Application Notes SZZA017 and SPRA953.

Copyright © 2015, Texas Instruments Incorporated

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