TPS65010RGZ datasheet(4/50 Pages) TI

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TPS65010

SLVS149A – JUNE 2003 – REVISED JANUARY 2004

ELECTRICAL CHARACTERISTICS (continued)

I(MAIN) = VI(CORE) = VCC = VI(LDO1) = VI(LDO2) = 3.6 V, TA = -40°C to 85°C, typical values are at TA = 25°C battery charger

specifications are valid in the range 0

°C < T

A < 85°C unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Delay after t(glitch) (PWRFAIL goes low)

t(batt_cover)

before supplies are disabled when

1.68

2.4

3.2

BATT_COVER goes low.

CONTROL SIGNALS: MPU_RESET, PWRFAIL, RESPWRON, INT, SDAT (output)

VOH

High level output voltage

VOL

Low level output voltage

IIL = 10 mA

0.3

td(mpu_nreset)

Duration of low pulse at MPU_RESET

100

µs

td(nrespwron)

Duration of low pulse at RESPWRON after

CHGCONFIG<7> = 0(Default)

800

1000

1200

VLDO1 is in regulation

CHGCONFIG<7> = 1

Time between UVLO going active

td(uvlo)

(PWRFAIL going low) and supplies being

1.68

2.4

3.2

disabled

Time between chip overtemperature con-

td(overtemp)

dition being recognized (PWRFAIL going

1.68

2.4

3.2

low) and supplies being disabled

SUPPLY PIN: VCC

I(Q)

Operating quiescent current

VI = 3.6 V, current into Main + Core + VCC

µA

VI = 3.6 V, BATT_COVER = GND,

IO(SD)

Shutdown supply current

µA

Current into Main + Core + VCC

VMAIN STEP-DOWN CONVERTER

Input voltage range

2.5

6.0

Maximum output current

1000

IO(SD)

Shutdown supply current

BATT_COVER = GND

0.1

µA

rDS(on)

P-channel MOSFET on-resistance

VI(MAIN) = VGS = 3.6 V

110

210

Ω

Ilkg(p)

P-channel leakage current

V(DS) = 6.0 V

µA

rDS(on)

N-channel MOSFET on-resistance

VI(MAIN) = VGS = 3.6 V

110

200

Ω

Ilkg(N)

N-channel leakage current

V(DS) = 6.0 V

µA

P-channel current limit

2.5 V< VI(MAIN) < 6.0 V

1.4

1.75

2.1

Oscillator frequency

1.25

1.5

MHz

VI(MAIN) = 2.7 V to 6.0 V; IO= 0 mA

2.5 V

VI(MAIN) = 2.7 V to 6.0 V;

0 mA

≤ I

O≤ 1000 mA

VI(MAIN) = 2.95 V to 6.0 V; IO= 0 mA

2.75 V

VI(MAIN) = 2.95 V to 6.0 V;

0 mA

≤ I

O≤ 1000 mA

VO(MAIN)

Fixed output voltage

VI(MAIN) = 3.2 V to 6.0 V; IO= 0 mA

3.0 V

VI(MAIN) = 3.2 V to 6.0 V;

0 mA

≤ I

O≤ 1000 mA

VI(MAIN) = 3.5 V to 6.0 V; IO= 0 mA

3.3 V

VI(MAIN) = 3.5 V to 6.0 V;

0 mA

≤ I

O≤ 1000 mA

VI(MAIN) = VO(MAIN) + 0.5 V (min. 2.5 V) to

Line regulation

0.5

%/V

6.0 V, IO = 10 mA

Load regulation

IO = 10 mA to 1000 mA

0.12

%/A

R(VMAIN)

VMAIN discharge resistance

400

Ω

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