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101 Datasheet(PDF) 1 Page - Silicon Laboratories

Part # 101
Description  NON-ISOLATED EVALUATION BOARD FOR THE Si3402B
PDF  13 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
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Rev. 1.1 4/16
Copyright © 2016 by Silicon Laboratories
Si3402B-EVB
Si3402B-EVB
N ON-I SOLATED E VALUATION B OARD FOR THE Si3402B
1. Description
The Si3402B non-isolated evaluation board (Si3402B-EVB Rev 2) is a reference design for a power supply in a
Power over Ethernet (PoE) Powered Device (PD) application. The Si3402B is described more completely in the
data sheet and application notes. This document describes the evaluation board. An evaluation board
demonstrating the isolated application is described in the Si3402B-ISO-EVB user’s guide.
2. Si3402B Board Interface
Ethernet data and power are applied to the board through the RJ45 connector (J1). The board itself has no
Ethernet data transmission functionality, but, as a convenience, the Ethernet transformer secondary is brought out
to the test points. Power may be applied in the following ways:
Connecting a dc source to pins 1, 2 and 3, 6 of the Ethernet cable (either polarity)
Connecting a dc source to pins 4, 5 and 7, 8 of the Ethernet cable (either polarity)
Using an IEEE 802.3-2015-compliant, PoE-capable PSE, such as Trendnet TPE-1020WS
The Si3402B-EVB board schematics and layout are shown in Figures 1 through 6. The dc output is at connectors
J11(+) and J12(–).
Boards are generally shipped configured to produce +5 V output voltage but can be configured for +3.3 V or other
output voltages by changing resistors R5 and R6. Refer to “AN956: Using the Si3402B PoE PD Controller in
Isolated and Non-Isolated Designs” for more information. The preconfigured Class 3 signature can also be
modified according to Table 3 in AN956. The D8–D15 Schottky type diode bridge bypass is recommended only for
higher power levels (Class 3 operation). For lower power levels, such as Class 1 and Class 2, the diodes can be
removed. When the Si3402B is used in external diode bridge configuration, it requires that at least one pair of the
CTx and SPx pins be connected to the PoE voltage input terminals (to the input of the external bridge).


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