Si3402B-EVB

10

Rev. 1.1

Introduction

Although the EVB design is pre-configured as a Class 3 PD with 5 V output, the schematics and layouts can easily

be adapted to meet a wide variety of common output voltages and power levels.

The

complete

EVB

design

databases

for

the

standard

5 V/Class 3

configuration

are

located

at

schematics and layout files as a starting point to ensure robust performance and avoid common mistakes in the

schematic capture and PCB layout processes.

Following are recommended design checklists that can assist in trouble-free development of robust PD designs.

Refer also to the Si3402B data sheet and AN956 when using the following checklists.

1. Design Planning Checklist:

a. Determine if your design requires an isolated or non-isolated topology. For more information, see

Section 4 of AN956.

b. Silicon Labs strongly recommends using the EVB schematics and layout files as a starting point as you

begin integrating the Si3402B into your system design process.

typical expected transient surge conditions). In general, to achieve the highest overall efficiency

performance of the Si3402B, choose the highest voltage used in your PD and then post regulate to the

lower supply rails, if necessary.

d. If your PD design consumes >7 W, be sure to bypass the Si3402B’s on-chip diode bridges with external

Schottky diode bridges or discrete diodes. Bypassing the Si3402B’s on-chip diode bridges with external

bridges or discrete Schottky diodes is required to help spread the heat generated in designs dissipating

>7W.

e. Based on your required PD power level, select the appropriate class resistor value by referring to Table 3

of AN956. This sets the Rclass resistor (R3 in Figure 1 on page 2).

2. General design checklist items:

a. ESD caps (C10–C17 in Figure 1) are strongly recommended for designs where system-level ESD

(IEC6100-4-2) must provide >15 kV tolerance.

b. If your design uses an AUX supply, be sure to include a 3 W surge limiting resistor in series with the AUX

supply for hot insertion. Refer to AN956 when AUX supply is 48 V.

c. Silicon Labs strongly recommends the inclusion of a minimum load (250 mW) to avoid switcher pulsing

when no load is present and to avoid false disconnection when less than 10 mA is drawn from the PSE.

If your load is not at least 250 mW, add a resistor load to dissipate at least 250 mW.

d. If using PLOSS function, make sure it’s properly terminated for connection in your PD subsystem. If

PLOSS is not needed, leave this pin floating.

3. Layout guidelines:

a. Make sure VNEG pin of the Si3402B is connected to the backside of the QFN package with an adequate

thermal plane, as noted in the data sheet and AN956.

b. Keep the trace length from connecting to SWO and retuning to Vss2 as short as possible. Make all of the

power (high current) traces as short, direct, and thick as possible. It is a good practice on a standard

PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per Ampere.

c. Usually, one standard via handles 200 mA of current. If the trace needs to conduct a significant amount

of current from one plane to the other, use multiple vias.