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CY7C343
Document #: 38-03015 Rev. *B
Page 9 of 19
fMAX2
Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 +
tCF)) or (1/tCO1)
[5, 16]
Com’l/Ind
43
33
MHz
Mil
43
33
fMAX3
Data Path Maximum Frequency, least of 1/(tWL + tWH), 1/(tS1 + tH),
or (1/tCO1)
[5, 17]
Com’l/Ind
50
40
MHz
Mil
50
40
fMAX4
Maximum Register Toggle Frequency (1/(tWL+tWH))
[5, 18]
Com’l/Ind
50
40
MHz
Mil
50
40
tOH
Output Data Stable Time from Synchronous Clock Input[5, 19]
Com’l/Ind
3
3
ns
Mil
3
3
tPW
Asynchronous Preset Width[5, 8]
Com’l/Ind
30
35
ns
Mil
30
35
External Asynchronous Switching Characteristics Over Operating Range [7]
Parameter
Description
7C343-20
7C343-25
Unit
Min.
Max.
Min.
Max.
tACO1
Asynchronous Clock Input to Output Delay[8]
Com’l/Ind
20
12
ns
Mil
20
tACO2
Asynchronous Clock Input to Local Feedback to Combinatorial
Output[20]
Com’l/Ind
32
25
ns
Mil
32
25
tAS1
Dedicated Input or Feedback Set-Up Time to Asynchronous
Clock Input[8]
Com’l/Ind
4
40
ns
Mil
4
40
tAS2
I/O Input Set-Up Time to Asynchronous Clock Input[8]
Com’l/Ind
15
5
ns
Mil
15
5
tAH
Input Hold Time from Asynchronous Clock Input[8]
Com’l/Ind
5
20
ns
Mil
5
20
tAWH
Asynchronous Clock Input HIGH Time[8]
Com’l/Ind
9
6
ns
Mil
9
6
tAWL
Asynchronous Clock Input LOW Time[8, 21]
Com’l/Ind
7
11
ns
Mil
7
11
tACF
Asynchronous Clock to Local Feedback Input[5, 22]
Com’l/Ind
13
9
ns
Mil
13
9
tAP
External Asynchronous Clock Period (1/fMAXA4)
[5]
Com’l/Ind
16
15
ns
Mil
16
15
fMAXA1
External Maximum Frequency in Asynchronous Mode 1/(tACO1
+ tAS1)
[5, 23]
Com’l/Ind
41.6
20
MHz
Mil
41.6
20
Notes:
20. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB
logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input.
The clock signal is applied to a dedicated input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material.
21. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped. If a
given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL.
22. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay
plus the asynchronous register set-up time, tAS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay is for feedback
within the same LAB, assumes no expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated input pin. This parameter is tested periodically
by sampling production material.
23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can
operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs, and that no expander logic is employed in the clock
signal path or data path.
External Synchronous Switching Characteristics Over Operating Range (continued)[7]
Parameter
Description
7C343-30
7C343-35
Unit
Min. Max. Min. Max.
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