DS2770

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1-WIRE INITIALIZATION SEQUENCE (RESET PULSE AND PRESENCE

PULSE) Figure 18

WRITE TIME SLOTS

A write time slot is initiated when the bus master pulls the 1-Wire bus from a logic high (inactive) level to

a logic low level. There are two types of write time slots: Write 1 and Write 0. All write time slots must

DS2770 samples the 1-Wire bus line between 15µs and 60µs after the line falls. If the line is high when

sampled, a Write 1 occurs. If the line is low when sampled, a Write 0 occurs (see Figure 19). For the bus

master to generate a Write 1 time slot, the bus line must be pulled low and then released, allowing the line

to be pulled high within 15µs after the start of the write time slot. For the host to generate a Write 0 time

slot, the bus line must be pulled low and held low for the duration of the write time slot.

READ TIME SLOTS

A read time slot is initiated when the bus master pulls the 1-Wire bus line from a logic high level to logic

low level. The bus master must keep the bus line low for at least 1µs and then release it to allow the

read time slot. By the end of the read time slot, the DS2770 releases the bus line and allows it to be pulled

GND

LINE TYPE LEGEND:

Bus master active low

DS2770 active low

Resistor pullup

Both bus master and

DS2770 active low

DQ