PC87365 datasheet(5/215 Pages) NSC

5 / 215 page

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Table of Contents

Datasheet Revision Record ................................................................................................................... 4

1.0

Signal/Pin Connection and Description

1.1

CONNECTION DIAGRAM ......................................................................................................... 14

1.2

BUFFER TYPES AND SIGNAL/PIN DIRECTORY .................................................................... 15

1.3

PIN MULTIPLEXING ................................................................................................................. 19

1.4

DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 21

1.4.1

ACCESS.bus Interface (ACB) .................................................................................... 21

1.4.2

Bus Interface ............................................................................................................... 21

1.4.3

Clock ............................................................................................................................ 21

1.4.4

Fan Speed Control and Monitor (FSCM) ..................................................................... 21

1.4.5

Floppy Disk Controller (FDC) ...................................................................................... 22

1.4.6

General-Purpose Input/Output (GPIO) Ports ............................................................... 23

1.4.7

Infrared (IR) ................................................................................................................. 23

1.4.8

Keyboard and Mouse Controller (KBC)

..................................................................... 24

1.4.9

Parallel Port

............................................................................................................... 24

1.4.10

Power and Ground ..................................................................................................... 25

1.4.11

Protection .................................................................................................................... 26

1.4.12

Serial Port 1 and Serial Port 2 ..................................................................................... 26

1.4.13

Strap Configuration ...................................................................................................... 27

1.4.14

System Hardware Monitoring ...................................................................................... 27

1.4.15

System Wake-Up Control ............................................................................................ 28

1.4.16

WATCHDOG Timer (WDT) ......................................................................................... 28

1.5

INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................ 29

2.0

Device Architecture and Configuration

2.1

OVERVIEW ............................................................................................................................... 31

2.2

CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 31

2.2.1

The Index-Data Register Pair ...................................................................................... 31

2.2.2

Banked Logical Device Registers Structure ................................................................ 33

2.2.3

Standard Logical Device Configuration Register Definitions ....................................... 34

2.2.4

Standard Configuration Registers ............................................................................... 36

2.2.5

Default Configuration Setup ........................................................................................ 37

2.2.6

Power States ...............................................................................................................38

2.2.7

Address Decoding ....................................................................................................... 38

2.3

INTERRUPT SERIALIZER ........................................................................................................ 38

2.4

PROTECTION ........................................................................................................................... 39

2.4.1

Chassis Intrusion Detection ......................................................................................... 39

2.4.2

Chassis Lock and Unlock ............................................................................................ 39

2.4.3

Access Lock to I/O Ports ............................................................................................. 40

2.4.4

Pin Configuration Lock ................................................................................................ 40

2.4.5

GPIO Pin Function Lock .............................................................................................. 40

PC87365 Datasheet(PDF) 5 Page - National Semiconductor (TI)

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