PC87365 datasheet(79/215 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.20 VOLTAGE LEVEL MONITOR (VLM) CONFIGURATION

2.20.1

Logical Device 13 (VLM) Configuration

Table 34 lists the configuration registers that affect the VLM. See Sections 2.2.3 and 2.2.4 for a detailed description of these

registers.

Table 34. VLM Conﬁguration Registers

2.21 TEMPERATURE SENSOR (TMS) CONFIGURATION

2.21.1

Logical Device 14 (TMS) Configuration

Table 35 lists the configuration registers that affect the TMS. See Sections 2.2.3 and 2.2.4 for a detailed description of these

registers.The OTS, ALERT, IRQ and SMI signals are routed through the configuration module. OTS is routed to a pin, IRQ

and SMI are routed to a designated interrupt signal and ALERT is not connected.

Table 35. TMS Conﬁguration Registers

Index

Conﬁguration Register or Action

Type

Reset

30h

Activate. When bit 0 is cleared, the registers of this logical device are not

accessible.

R/W

00h

60h

Base Address MSB register

R/W

00h

61h

Base Address LSB register. Bits 3-0 (for A3-0) are read only, 0000b.

R/W

00h

70h

Interrupt Number

R/W

00h

71h

Interrupt Type. Bit 1 is read/write. Other bits are read only.

R/W

03h

74h

Report no DMA assignment

04h

75h

Report no DMA assignment

04h

Index

Conﬁguration Register or Action

Type

Reset

30h

Activate. When bit 0 is cleared, the registers of this logical device are not

accessible.

R/W

00h

60h

Base Address MSB register

R/W

00h

61h

Base Address LSB register. Bits 3-0 (for A3-0) are read only, 0000b.

R/W

00h

70h

Interrupt Number

R/W

00h

71h

Interrupt Type. Bit 1 is read/write. Other bits are read only.

R/W

03h

74h

Report no DMA assignment

04h

75h

Report no DMA assignment

04h

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