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6.0 General-Purpose Input/Output (GPIO) Port (Continued)

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6.4.2

GPIO Pin Event Routing (GPEVR) Register

This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is

mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register, which functions as an index

register and the specific GPER register, which reflects the routing configuration of the currently selected pin. For details on

the GPSEL register, refer to the

Device Architecture and Configuration chapter.

This set of registers is applicable only for the enhanced GPIO port with event detection support. In the basic port, this register

set is reserved, returns 0 on read and has no effect on port functionality.

Location:

Device specific

Type:

R/W

6.4.3

GPIO Port Runtime Register Map

Bit

76543210

Name

Reserved

GPIO Event

to PWUREQ

Enable

GPIO Event

to SMI En-

able

GPIO Event

to IRQ En-

able

Reset

00000001

Bit

Description

7-3

Reserved.

GPIO Event to PWUREQ Enable. This bit is used to enable/disable the routing of the corresponding GPIO

detected event to PWUREQ.

0: Disabled (default)

1: Enabled

GPIO Event to SMI Enable. This bit is used to enable/disable the routing of the corresponding GIO detected

event to SMI.

0: Disabled (default)

1: Enabled

GPIO Event to IRQ Enable. This bit is used to enable/disable the routing of the corresponding GPIO detected

event to IRQ.

0: Disabled

1: Enabled (default)

Offset

Mnemonic

Type

Section

Device speciﬁc1

The location of this register is deﬁned in the

Device Architecture and Conﬁguration

chapter in Section 2.16.1.

GPDO

GPIO Data Out

R/W

6.4.4

Device speciﬁc1

GPDI

GPIO Data In

6.4.5

Device speciﬁc1

GPEVEN

GPIO Event Enable

R/W

6.4.6

Device speciﬁc1

GPEVST

GPIO Event Status

R/W1C

6.4.7

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