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8

PS8450B

04/09/01

PI6C3991

3.3V High-Speed, Low-Voltage Programmable

Figure 3 shows a configuration to equalize skew between metal

traces of different lengths. In addition to low skew between outputs,

the SuperClock can be programmed to stagger the timing of its

outputs. The four groups of output pairs can each be programmed

to different output timing. Skew timing can be adjusted over a wide

range in small increments with the appropriate strapping of the

function select pins. In this configuration the 4Q0 output is fed back

to FB and configured for zero skew.

The other three pairs of outputs are programmed to yield different

skews relative to the feedback. By advancing the clock signal on the

longer traces or retarding the clock signal on shorter traces, all loads

can receive the clock pulse at the same time.

In this illustration the FB input is connected to an output with 0ns

skew(xF1,xF0=MID)selected.TheinternalPLLsynchronizesthe

FB and REF inputs and aligns their rising edges to insure that all

outputs have precise phase alignment.

output selected for zero skew as the feedback. A wider range of

delaysispossibleiftheoutputconnectedtoFBisalsoskewed.Since

since the PLL aligns the rising edges of REF and FB, it is possible to

create wider output skews by proper selection of the xFn inputs. For

ing 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 =

skewing both the output used as the FB input and skewing the other

outputs.

Figure4.InvertedOutputConnections

FB

REF

FS

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

TEST

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

REF

Figure 4 shows an example of the invert function of the SuperClock.

In this example the 4Q0 output used as the FB input is programmed

for invert (4F0 = 4F1 = HIGH) while the other three pairs of outputs

areprogrammedforzeroskew.When4F0and4F1aretiedHIGH,4Q0

and 4Q1 become inverted zero phase outputs. The PLL aligns the

rising edge of the FB input with the rising edge of the REF. This

causes the 1Q, 2Q, and 3Q outputs to become the “inverted” outputs

with respect to the REF input. By selecting which output is connect

to FB, it is possible to have 2 inverted and 6 non-inverted outputs

or6invertedand2non-invertedoutputs.Thecorrectconfigura-tion

would be determined by the need for more (or fewer) inverted

outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate

for varying trace delays independent of inver-sion on 4Q.

Figure5.FrequencyMultiplierwithSkewConnections

FB

REF

FS

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

TEST

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

REF

20 MHz

40 MHz

20 MHz

80 MHz

Figure 5 illustrates the SuperClock configured as a clock multiplier.

The 3Q0 output is programmed to divide by four and is fed back to

FB. This causes the PLL to increase its frequency until the 3Q0 and

3Q1outputsarelockedat20MHzwhilethe1Qxand2Qxoutputsrun

at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by

two, which results in a 40 MHz waveform at these outputs. Note that

the 20 and 40 MHz clocks fall simultaneously and are out of phase

on their rising edge. This will allow the designer to use the rising

edges of the ½ frequency and ¼ frequency outputs without concern

forrising-edgeskew.The2Q0,2Q1,1Q0,and1Q1outputsrunat80

MHz and are skewed by programming their select inputs accord-

ingly.NotethattheFSpiniswiredfor80MHzoperationbecausethat

is the frequency of the fastest output.