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PI6C3991

3.3V High-Speed, Low-Voltage Programmable

3

PS8450B

04/09/01

FB Input

REF Input

(N/A)

HH

Invert

(N/A) LL/HH Divided

(N/A)

LM

LL

LH

LM

(N/A)

LH

ML

ML

(N/A)

MM

MM

MH

(N/A)

HL

MH

HM

(N/A)

HH

HL

(N/A)

HM

1Fx

2Fx

3Fx

4Fx

Figure1.TypicalOutputswithFBConnectedtoa

Note:

3. FB connected to an output selected for "zero" skew

(ie.,xF1=xF0=MID).

Block Diagram Description

Phase Frequency Detector and Filter

These two blocks accept input signals from the reference frequency

(REF) input and the feedback (FB) input and generate correction

information to control the frequency of the Voltage-Controlled

Oscillator (VCO). These blocks, along with the VCO, form a Phase-

Locked Loop (PLL) that tracks the incoming REF signal.

VCO and Time Unit Generator

The VCO accepts analog control inputs from the PLL filter block

and generates a frequency that is used by the time unit generator

to create discrete time units that are selected in the skew mix matrix.

The operational range of the VCO is determined by the FS control

the device and the level of the FS pin as shown in Table 1.

Skew Select Matrix

The skew select matrix is comprised of four independent sections.

Each section has two low-skew, high-fanout drivers (xQ0, xQ1),

and two corresponding three-level function select (xF0, xF1)

inputs. Table 2 shows the nine possible output functions for each

section as determined by the function select inputs. All times are

measured with respect to the REF input assuming that the output

e

g

n

a

Re

r

u

t

a

r

e

p

m

e

T

t

n

e

i

b

m

C

l

ai

c

r

e

m

m

o

CC

°

0

7

+

o

t

C

°

0%

0

1

±

V

3

.

3

l

ai

rt

s

u

d

n

IC

°

5

8

+

o

t

C

°

0

4

–%

0

1

±

V

3

.

3

Test Mode

The TEST input is a three-level input. In normal system operation,

this pin is connected to ground, allowing the PI6C3991 to operate

as explained briefly above (for testing purposes, any of the three

level inputs can have a removablejumper to ground, or be tied LOW

through a 100 Ohm resistor. This will allow an external tester to

change the state of these pins.)

If the TEST input is forced to its MID or HIGH state, the device will

operate with its internal phase locked loop disconnected, and input

levels supplied to REF will directly control all outputs. Relative

output to output functions are the same as in normal mode.

In contrast with normal operation (TEST tied LOW). All outputs

will function based only on the connection of their own function

select inputs (xF0 and xF1) and the waveform characteristics of

the REF input.

Storage Temperature ...................................... –65°Cto+150°C

Ambient Temperature with

Power Applied .................................................–55°Cto+125°C

Supply Voltage to Ground Potential .................. –0.5Vto+7.0V

DC Input Voltage ...............................................–0.5Vto+7.0V

Output Current into Outputs (LOW) ............................... 64mA

Static Discharge Voltage ............................................... >2001V

(perMIL-STD-883,Method3015)

Latch-UpCurrent ......................................................... >200mA

MaximumRatings

OperatingRange