Definition of Terms

Hold Step: The voltage step at the output of the sample and

hold when switching from sample mode to hold mode with a

steady (dc) analog input voltage. Logic swing is 5V.

Acquisition Time: The time required to acquire a new ana-

log input voltage with an output step of 10V. Note that acqui-

sition time is not just the time required for the output to settle,

but also includes the time required for all internal nodes to

settle so that the output assumes the proper value when

switched to the hold mode.

Gain Error: The ratio of output voltage swing to input volt-

age swing in the sample mode expressed as a per cent dif-

ference.

Hold Settling Time: The time required for the output to

settle within 1 mV of final value after the “hold” logic com-

mand.

Dynamic Sampling Error: The error introduced into the

held output due to a changing analog input at the time the

hold command is given. Error is expressed in mV with a

given hold capacitor value and input slew rate. Note that this

error term occurs even for long sample times.

Aperture Time: The delay required between “Hold” com-

mand and an input analog transition, so that the transition

does not affect the held output.

Connection Diagrams

Differential Hold

DS005692-57

Capacitor Hysteresis Compensation

DS005692-56

**Adjust for amplitude

Dual-In-Line Package

DS005692-11

Order Number LF398N

or LF398AN

See NS Package Number N08E

Small-Outline Package

DS005692-15

Order Number LF298M or LF398M

See NS Package Number M14A

Metal Can Package

DS005692-14

Order Number LF198H,

LF198H/883, LF298H,

LF398H, LF198AH or LF398AH

See NS Package Number H08C

(Note 8)

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