T2803 datasheet(20/27 Pages) ATMEL

Part #	T2803

Description	2.4 GHZ WDECT/ISM SINGLE CHIP TRANSCEIVER

PDF	27 Pages

Scroll/Zoom	100%

Manufacturer	ATMEL [ATMEL Corporation]

Direct Link	http://www.atmel.com

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20 / 27 page

T2803 [Preliminary]

4572G–DECT–01/04

Output Power Settings

With bits E11 - E12

Use of maximum power (+3 dBm) for external PA is recommended.

Figure 4. 3-wire Bus Protocol Timing Diagram

Table 5. 3-wire bus Protocol Table

Figure 5. TX DATA Timing

PA (Output Power Settings)

E12

E11

-21 dBm

-11 dBm

-4 dBm

+3 dBm

DATA

CLOCK

ENABLE

TEC

TPER

16525

Description

Symbol

Minimum Value

Unit

Clock period

TPER

125

Set time data to clock

Hold time data to clock

Clock pulse width

125

Set time enable to clock

200

Hold time enable to data

TEC

Time between two protocols

250

RefCLK

TX_DATA

Set-up time TX DATA

> 8 ns

When using REFCLK = 10.368 MHz, TS and TH must be

considered for falling and rising edge of REFCLK

Hold time TX DATA

> 8 ns

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