TPS40052

SLUS563B − AUGUST 2003 − REVISED APRIL 2004

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LAYOUT CONSIDERATIONS

Grounding and Circuit Layout Considerations

The TPS4005x provides separate signal ground (SGND) and power ground (PGND) pins. It is important that

circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if

possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling

capacitor (BP10), and the input capacitor should be connected to PGND plane at the input capacitor.

SGND plane should only make a single point connection to the PGND plane.

Component placement should ensure that bypass capacitors (BP10 and BP5) are located as close as possible

to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located

near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW).

The SW pin Schottky diode, D2 in Figure 10, should be placed close to the TPS40052 with short, wide traces

to pins 9 and 12.