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AD9823 Datasheet(PDF) 4 Page - Analog Devices

Part # AD9823
Description  Correlated Double Sampler (CDS)
PDF  8 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9823 Datasheet(HTML) 4 Page - Analog Devices

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AD9823
Rev. 0 | Page 4 of 8
TIMING SPECIFICATIONS
Table 4. TMIN to TMAX, VDD = 3.0 V, fSAMP = 40 MHz, unless otherwise noted.
Parameter (See Figure 3)
Symbol
Min
Typ
Max
Unit
Sample Clocks
SHP, SHD Clock Period
tCP
25
ns
SHP Pulse Width
tSHP
5
6.25
ns
SHD Pulse Width
tSHD
5
6.25
ns
CLP Pulse Width1
tCOB
4
10
pixels
SHP Rising Edge to SHD Rising Edge
tS1
12.0
12.5
ns
SHD Rising Edge to SHP Rising Edge
tS2
12.0
12.5
ns
Internal Clock Delay
tID
3.0
ns
Recommended Data CLK Timing (for AD9821)
tREC
4.5
ns
1 Minimum CLP pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance. Specifications subject to
change without notice.



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