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TPS65217 Datasheet(PDF) 21 Page - Texas Instruments

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Part # TPS65217
Description  Single-Chip PMIC for Battery-Powered Systems
PDF  89 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS65217 Datasheet(HTML) 21 Page - Texas Instruments

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TPS65217
www.ti.com
SLVSB64G – NOVEMBER 2011 – REVISED JANUARY 2015
Feature Description (continued)
9.3.1.3 Special Strobes (STROBE 14 and 15)
STROBE 14 and STORBE 15 are not assigned to the main sequencer but used to control rails that are ‘always-
on’, i.e. are powered up as soon as the device exits OFF state and remain ON in SLEEP state. STROBE 14/15
options are available only for LDO1 and LDO2 and not for any of the other rails.
STROBE 14 occurs as soon as the push-button is pressed or the USB or AC adaptor is connected to the device.
After a delay time of DLY6 STROBE 15 occurs. LDO1 and LDO2 can be assigned to either strobe and therefore
can be powered up in any order (contact factory for details - default settings must be factory programmed since
all registers are reset in SLEEP mode).
When a power-down sequence is initiated, STOBE 15 and STOBE 14 will occur only if the OFF bit is set.
Otherwise both strobes are omitted and LDO1 and LDO2 will maintain state.
9.3.2 Power Good
Power-good is a signal used to indicate if an output rail is in regulation or at fault. Internally, all power-good
signals of the enabled rails are monitored at all times and if any of the signals goes low, a fault is declared. All
PGOOD signals are internally deglitched. When a fault occurs, all output rails are powered down and the device
enters OFF state.
The TPS65217 has two PGOOD outputs, one dedicated to LDO1 and 2 (LDO_PGOOD), and one programmable
output (PGOOD). The following rules apply to both outputs:
•
The power-up default state for PGOOD/LDO_PGOOD is low. When all rails are disabled, PGOOD and
LDO_PGOOD outputs are both low.
•
Only enabled rails are monitored. Disabled rails are ignored.
•
Power-good monitoring of a particular rail starts 5ms after the rail has been enabled. It is continuously
monitored thereafter. This allows the rail to power-up.
•
PGOOD and LDO_PGOOD outputs are delayed by the PGDLY (20 ms default) after the sequencer is done.
•
If an enabled rail goes down due to a fault (output shorted, OTS, UVLO), PGOOD and/or LDO_PGOOD is
declared low, and all rails are shut-down.
•
If the user disables a rail (either manually or through sequencer), it has no effect on the PGOOD or
LDO_PGOOD pin.
•
If the user disables all rails (either manually or through sequencer) PGOOD and/or LDO_PGOOD will be
pulled low.
9.3.2.1 LDO1, LDO2 PGOOD (LDO_PGOOD)
LDO_PGOOD is a push-pull output which is driven to high-level whenever LDO1 and/or LDO2 are enabled and
in regulation. It is pulled low when both LDOs are disabled or at least one is enabled but has encountered a fault.
A typical fault is an output short or over-current condition. In normal operation LDO_PGOOD is high in ACTIVE
and SLEEP state and low in RESET or OFF state.
9.3.2.2 Main PGOOD (PGOOD)
The main PGOOD pin has similar functionality to the LDO_PGOOD pin except that it monitors DCDC1, DCDC2,
DCDC3, and LS1/LDO3, LS2/LDO4 if they are configured as LDOs. If LS1/LDO3 and/or LS2/LDO4 are
configured as load switches, their respective PGOOD status is ignored. In addition, the user can choose to also
monitor LDO1 and LDO2 by setting the LDO1PGM and LDO2PGM bits in the DEFPG register low. By default,
LDO1 and LDO2 PGOOD status does not affect the PGOOD pin (mask bits are set to 1 by default). In normal
operation PGOOD is high in ACTIVE state but low in SLEEP, RESET or OFF state.
In SLEEP mode and WAIT PWR_EN state, PGOOD pin is forced low. PGOOD is pulled high after entering
ACTIVE mode, the power sequencer done, and the PGDLY expired. This function can be disabled by the factory.
9.3.2.3 Load Switch PGOOD
If either LS1/LDO3 or LS2/LDO4 are configured as load switches their respective PGOOD signal is ignored by
the system. An over-current or short condition will not affect the PGOOD pin or any of the power rails unless the
power dissipation leads to thermal shut-down.
Copyright © 2011–2015, Texas Instruments Incorporated
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