CDCFR83

DIRECT RAMBUS

 CLOCK GENERATOR

SCAS665A – APRIL 2001 REVISED MARCH 2002

8

POST OFFICE BOX 655303

state transition latency specifications (continued)

PARAMETER

FROM

TO

TEST

CONDITIONS

MIN

TYP†

MAX

UNIT

t(powerdown)

Delay time, PWRDNB

↓ to the device in the

power-down mode

Normal

Powerdown

See Figure 8

1

ms

t(STOP)

Maximum time in CLKSTOP (STOPB = 0)

before reentering normal mode

(STOPB = 1)

STOPB

Normal

See Figure 10

100

µs

t(ON)

Minimum time in normal mode (STOPB = 1)

before reentering CLKSTOP (STOPB = 0)

Normal

CLK stop

See Figure 10

100

ms

t(DISTLOCK)

Time from when CLK/CLKB output is

settled to when the phase error between

SYNCLKN and PCLKM falls within t(phase)

Unlocked

Locked

5

ms

† All typical values are at VDD = 3.3 V, TA = 25°C.

PARAMETER MEASUREMENT INFORMATION

39

Ω, ±5%

68

Ω, ±5%

68

Ω, ±5%

10 pF

100 pF

39

Ω, ±5%

10 pF

RT = 28 Ω

RT = 28 Ω

CLK

CLKB

tc(1)

tc(2)

Cycle-to-cycle jitter = | tc(1) – tc(2)| over 10000 consecutive cycles

Figure 2. Cycle-to-Cycle Jitter