CY28343
Document #: 38-07369 Rev. *A
Page 2 of 10
Notes:
2.
PU = internal pull-up PD = internal pull-down.
3.
A bypass capacitor (0.1 mF) should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their
high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Power Management
The individual output enable/disable control of the CY28343
allows the user to implement unique power management
schemes into the design. Outputs are in LOW state when dis-
abled through the two-line interface as individual bits are set
LOW in Byte0 to Byte2 registers. The feedback output
FBOUT_DDR and FBOUT_SDR cannot be disabled via
two-line serial bus.
Zero Delay Buffer
When used as a ZERO delay buffer the CY28343 will likely be
in a nested clock tree application. For these applications the
CY28343 offers single-end input as a PLL reference. The
CY28343 then can lock onto the reference and translate with
near zero to low-skew outputs. For normal operation, the ex-
ternal feedback input, FBIN_DDR and FBIN_SDR, are con-
nected
to
the
feedback
output,
FBOUT_DDR
and
FBOUT_SDR. By connecting the feedback output to the feed-
back input the propagation delay through the device is elimi-
nated. The PLL works to align the output edge with the input
reference edge thus producing a near zero delay. The refer-
ence frequency affects the static phase offset of the PLL and
thus the relative delay between the inputs and outputs.
Pin Description[2, 3]
Pin
Name
I/O
Description
10
CLKIN
I
Clock Input. Reference the PLL
47
FBIN_DDR
I
PD
Feedback Clock Output. Connect to FBOUT_DDR for accessing the PLL.
See Function Table on page 1
23
FBIN_SDR
I
PD
Feedback Clock Input. Connect to FBOUT_SDR for accessing the PLL. See
Function Table on page 1
30,32,36,38
42,44
DDRT(0:5)
O
Clock Outputs. True copies of the CLKIN input
29,31,35,37
41,43
DDRC(0:5)
O
Clock Outputs. Complementary copies of the CLKIN input
2-5,8,9
15-18,21
SDRAM(0:12)
O
Clock Outputs. True copies of the CLKIN input
46
FBOUT_DDR
O
Feedback Clock Output. Connect to FBIN_DDR for normal operation. A true
copy of the CLKIN input. The delay of the PCB trace RC at this output will
control Input Reference/DDR Output Clocks phase relationships.
22
FBOUT_SDR
O
Feedback Clock Output. Connect to FBIN_SDR for normal operation. A true
copy of the CLKIN input. The delay of the PCB trace RC at this output will
control Input Reference/ SDR Output Clocks phase relationships.
48
SELDDR_SDR#
I
PD
SDR or DDR Select Pin. See Function Table on page 1
26
SCLK
I
PU
Serial Clock Input. Clocks data at SDATA into the internal register.
25
SDATA
I/O
PU
Serial Data Input. Input data is clocked to the internal register to enable/disable
individual outputs. This provides flexibility in power management.
1,7,14,20,27
VDD_3.3V
3.3V power supply for SDR outputs and two line serial Interface
33,39,45
VDD_2.5V
2.5V power supply for DDR outputs
6,13,19,24,28
,34,40
VSS
Common Ground
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