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CY28343OC Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY28343OC
Description  Zero Delay SDR/DDR Clock Buffer
PDF  10 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY28343OC Datasheet(HTML) 4 Page - Cypress Semiconductor

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CY28343
Document #: 38-07369 Rev. *A
Page 4 of 10
Note:
4.
These bits will be ignored in DDR mode. See Table 1 on page 1.
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address – 7 bits
2:8
Slave address – 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code - 8 bits'1xxxxxxx' stands for
byte operationbit[6:0] of the command code rep-
resents the offset of the byte to be accessed
11:18
Command Code – 8 bits'1xxxxxxx' stands for
byte operationbit[6:0] of the command code rep-
resents the offset of the byte to be accessed
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Byte Count – 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address – 7 bits
29
stop
28
Read
29
Acknowledge from slave
30:37
Data byte from slave – 8 bits
38
Not Acknowledge
39
stop
Byte 0: Output Register (1 = Enable, 0 = Disable)[4]
Bit
@Pup
Pin #
Description
7
1
29,30
DDRT/C0. 1 = Enable, 0 = Output disabled asynchronously in a low state
6
1
31,32
DDRT/C1. 1 = Enable, 0 = Output disabled asynchronously in a low state
5
1
35,36
DDRT/C2. 1 = Enable, 0 = Output disabled asynchronously in a low state
4
1
37,38
DDRT/C3. 1 = Enable, 0 = Output disabled asynchronously in a low state
3
1
41,42
DDRT/C4. 1 = Enable, 0 = Output disabled asynchronously in a low state
2
1
43,44
DDRT/C5. 1 = Enable, 0 = Output disabled asynchronously in a low state
11
Reserved
0
1
48
SELDDR_DDR hardware setting value. Read only.
Byte 1: Output Register (1 = Enable, 0 = Disable)[4]
Bit
@Pup
Pin #
Description
7
1
12
SDRAM7. 1 = Enable, 0 = Output disabled asynchronously in a low state
6
1
11
SDRAM6. 1 = Enable, 0 = Output disabled asynchronously in a low state
5
1
9
SDRAM5. 1 = Enable, 0 = Output disabled asynchronously in a low state
4
1
8
SDRAM4. 1 = Enable, 0 = Output disabled asynchronously in a low state
3
1
5
SDRAM3. 1 = Enable, 0 = Output disabled asynchronously in a low state
2
1
4
SDRAM2. 1 = Enable, 0 = Output disabled asynchronously in a low state
1
1
3
SDRAM1. 1 = Enable, 0 = Output disabled asynchronously in a low state
0
1
2
SDRAM0. 1 = Enable, 0 = Output disabled asynchronously in a low state



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