TUSB8020B datasheet(32/43 Pages) TI1

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TUSB8020B

SLLSEF6A – JULY 2014 – REVISED JULY 2014

www.ti.com

11 Layout

11.1 Layout Guidelines

11.1.1 Placement

1. A 9.53-k

Ω ±1% resistor connected to terminal USB_R1 should be placed as close as possible to the

TUSB8020B.

2. A 0.1-µF capacitor should be placed as close as possible on each VDD and VDD33 power pin.

3. The 100-nF capacitors on the SSTXP and SSTXM nets should be placed close to the USB connector (type

A, type B, and so forth).

4. The ESD and EMI protection devices (if used) should also be placed as possible to the USB connector.

5. If a crystal is used, it must be placed as close as possible to the TUSB8020B device’s XI and XO terminals.

6. Place voltage regulators as far away as possible from the TUSB8020B, crystal, and differential pairs.

7. In general, the large bulk capacitors associated with each power rail should be placed as close as possible to

the voltage regulators.

11.1.2 Package Specific

1. The TUSB8020B package has a 0.5-mm pin pitch.

2. The TUSB8020B package has a 3.6-mm × 3.6-mm thermal pad. This thermal pad must be connected to

ground through a system of vias.

3. All vias under device, except for those connected to thermal pad, should be solder masked to avoid potential

issues with thermal pad layouts.

11.1.3 Differential Pairs

This section describes the layout recommendations for all of the TUSB8020B differential pairs: USB_DP_XX,

USB_DM_XX, USB_SSTXP_XX, USB_SSTXM_XX, USB_SSRXP_XX, and USB_SSRXM_XX.

•

Must be designed with a differential impedance of 90

Ω ±10%.

•

To minimize crosstalk, TI recommends to keep high-speed signals away from each other. Each pair should

be separated by at least 5× the signal trace width. Separating with ground as depicted in the layout example

also helps minimize crosstalk.

•

Route all differential pairs on the same layer adjacent to a solid ground plane.

•

Do not route differential pairs over any plane split.

•

Adding test points causes impedance discontinuity, and therefore, negatively impacts signal performance. If

test points are used, they should be placed in series and symmetrically. They must not be placed in a manner

that causes stub on the differential pair.

•

Avoid 90° turns in trace. The use of bends in differential traces should be kept to a minimum. When bends

are used, the number of left and right bends should be as equal as possible and the angle of the bend should

≥135°. Taking this action minimizes any length mismatch caused by the bends, and therefore, minimizes

the impact bends have on EMI.

•

Minimize the trace lengths of the differential pair traces. Eight inches is the maximum recommended trace

length for SS differential-pair signals and USB 2.0 differential-pair signals. Longer trace lengths require very

careful routing to assure proper signal integrity.

•

Match the etch lengths of the differential pair traces (that is DP and DM or SSRXP and SSRXM or SSTXP

and SSTXM). There should be less than 5-mils difference between a SS differential-pair signal and its

complement. The USB 2.0 differential pairs should not exceed 50-mils relative trace length difference.

•

The etch lengths of the differential pair groups do not need to match (that is the length of the SSRX pair to

that of the SSTX pair), but all trace lengths should be minimized.

•

Minimize the use of vias in the differential-pair paths as much as possible. If this is not practical, ensure that

the same via type and placement are used for both signals in a pair. Any vias used should be placed as close

as possible to the TUSB8020B device.

•

To ease routing, the polarity of the SS differential pairs can be swapped. This means that SSTXP can be

routed to SSTXM or SSRXM can be routed to SSRXP.

•

Do not place power fuses across the differential-pair traces.

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