ST92196A datasheet(133/268 Pages) STMICROELECTRONICS

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- ON SCREEN DISPLAY CONTROLLER (OSD)

OSD CONTROLLER (Cont’d)

8.5.6.2 Underline Color Set 2 (UCS2)

Address in Segment 22h: 06h (Bits 15:8), 07h (Bits 7:0)

Bits 15:12 = Free for the user

Bits 11:9 = U2T[2:0]

Underline color set 1 Translu-

cency

These bits configure the background translucency

level applied to the color (refer to Section 8.5.3.11

for more details).

U2T[2:0] = 7 means that this color will be fully

opaque (no video mixed in it on the display)

U2T[2:0] = 0 means that this color will be fully

transparent (the video is displayed instead of this

color)

Bits 8:6 = U2R[2:0]

Underline color set 1 Red

color

These bits configure the background red intensity

for the color.

U2R[2:0] = 0 means that no red is used to define

the color.

U2R[2:0] = 7 means that the maximum red intensi-

ty is used in the color.

Bits 5:3 = U2G[2:0]

Underline color set 1 Green

color

These bits configure the background green inten-

sity for the color.

U2G[2:0] = 0 means that no green is used to de-

fine the color.

U2G[2:0] = 7 means that the maximum green in-

tensity is used in the color.

Bits 2:0 = U2B[2:0]

Underline color set 1 Blue

color

These bits configure the background blue intensity

for the color.

U2B[2:0] = 0 means that no blue is used to define

the color.

U2B[2:0] = 7 means that the maximum blue inten-

sity is used in the color.

Warning: The UCS1 and UCS2 data may be used

as “row attributes” providing more than 3 underline

colors on screen. This requires taking some care

when their contents are modified.

The UCS1 and UCS2 contents are fetched for dis-

play only when dot lines 12/13 of the character are

being processed, but at that time (while dot lines

12 and 13 are processed) any change to UCS1 or

UCS2 is forbidden.

Software should change the UCS1 or UCS2 while

the display processes character dot lines 1 to 11. It

is recommended to associate the UCS1 or UCS2

management of the currently displayed buffer with

the routine which handles the next buffer prepara-

tion. Refer to Section 8.5.8.9.

U2T2

U2T1

U2T0

U2R2 U2R1

U2R0

U2G2

U2G1

U2G0

U2B2

U2B1

U2B0

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