ST92196A datasheet(56/268 Pages) STMICROELECTRONICS

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INTERRUPTS

INTERRUPT REGISTERS (Cont’d)

EXTERNAL INTERRUPT TRIGGER REGISTER

(EITR)

R242 - Read/Write

Reset value: 0000 0000 (00h)

Bit 7 = TED1:

INTD1 Trigger Event

Bit 6 = TED0:

INTD0 Trigger Event

Bit 5 = TEC1:

INTC1 Trigger Event

Bit 4 = TEC0:

INTC0 Trigger Event

Bit 3 = TEB1:

INTB1 Trigger Event

Bit 2 = TEB0:

INTB0 Trigger Event

Bit 1 = TEA1:

INTA1 Trigger Event

Bit 0 = TEA0:

INTA0 Trigger Event

These bits are set and cleared by software.

0: Select falling edge as interrupt trigger event

1: Select rising edge as interrupt trigger event

EXTERNAL INTERRUPT PENDING REGISTER

(EIPR)

R243 - Read/Write

Reset value: 0000 0000 (00h)

Bit 7 = IPD1:

INTD1 Interrupt Pending bit

Bit 6 = IPD0:

INTD0 Interrupt Pending bit

Bit 5 = IPC1:

INTC1 Interrupt Pending bit

Bit 4 = IPC0:

INTC0 Interrupt Pending bit

Bit 3 = IPB1:

INTB1 Interrupt Pending bit

Bit 2 = IPB0:

INTB0 Interrupt Pending bit

Bit 1 = IPA1:

INTA1 Interrupt Pending bit

Bit 0 = IPA0:

INTA0 Interrupt Pending bit

These bits are set by hardware on occurrence of a

trigger event (as specified in the EITR register)

and are cleared by hardware on interrupt acknowl-

edge. They can also be set by software to imple-

ment a software interrupt.

0: No interrupt pending

1: Interrupt pending

EXTERNAL INTERRUPT MASK-BIT REGISTER

(EIMR)

R244 - Read/Write

Reset value: 0000 0000 (00h)

Bit 7 = IMD1:

INTD1 Interrupt Mask

Bit 6 = IMD0:

INTD0 Interrupt Mask

Bit 5 = IMC1:

INTC1 Interrupt Mask

Bit 4 = IMC0:

INTC0 Interrupt Mask

Bit 3 = IMB1:

INTB1 Interrupt Mask

Bit 2 = IMB0:

INTB0 Interrupt Mask

Bit 1 = IMA1:

INTA1 Interrupt Mask

Bit 0 = IMA0:

INTA0 Interrupt Mask

These bits are set and cleared by software.

0: Interrupt masked

1: Interrupt not masked (an interrupt is generated if

the IPxx and IEN bits = 1)

TED1 TED0 TEC1 TEC0 TEB1 TEB0 TEA1 TEA0

IPD1

IPD0

IPC1

IPC0

IPB1

IPB0

IPA1

IPA0

IMD1 IMD0 IMC1 IMC0 IMB1 IMB0 IMA1 IMA0

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