ST92196A datasheet(43/268 Pages) STMICROELECTRONICS

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INTERRUPTS

3 INTERRUPTS

3.1 INTRODUCTION

The ST9 responds to peripheral and external

events through its interrupt channels. Current pro-

gram execution can be suspended to allow the

ST9 to execute a specific response routine when

such an event occurs, providing that interrupts

have been enabled, and according to a priority

mechanism. If an event generates a valid interrupt

request, the current program status is saved and

control passes to the appropriate Interrupt Service

Routine.

The ST9 CPU can receive requests from the fol-

lowing sources:

– On-chip peripherals

– External pins

– Top-Level Pseudo-non-maskable interrupt

According to the on-chip peripheral features, an

event occurrence can generate an Interrupt re-

quest which depends on the selected mode.

Up to eight external interrupt channels, with pro-

grammable input trigger edge, are available. In ad-

dition, a dedicated interrupt channel, set to the

Top-level priority, can be devoted either to the ex-

ternal NMI pin (where available) to provide a Non-

Maskable Interrupt, or to the Timer/Watchdog. In-

terrupt service routines are addressed through a

vector table mapped in Memory.

Figure 17. Interrupt Response

NORMAL

PROGRAM

FLOW

INTERRUPT

SERVICE

ROUTINE

IRET

INSTRUCTION

INTERRUPT

VR001833

CLEAR

PENDING BIT

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