TFP401, TFP401A

TI PanelBus

 DIGITAL RECEIVER

SLDS120B - MARCH 2000 – REVISED JUNE 2003

7

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

ac specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VID(2)

Differential input sensitivity†

150

1560

mVp-p

tps

Analog input intra-pair (+ to -) differen-

tial skew (see Note 6)

0.4

tbit‡

tccs

Analog Input inter-pair or channel-to-

channel skew (see Note 6)

1

tpix§

tijit

Worse case differential input clock jitter

tolerance¶ (see Note 6)

50

ps

tf1

Fall time of data and control signals#, ||

ST = Low,

CL=5 pF

ST = High,

CL=10 pF

2.4

1.9

ns

tr1

Rise time of data and control signals#, ||

ST = Low,

CL=5 pF

ST = High,

CL=10 pF

2.4

1.9

ns

tr2

Rise time of ODCK clock#

ST = Low,

CL=5 pF

ST = High,

CL=10 pF

2.4

1.9

ns

tf2

Fall time of ODCK clock#

ST = Low,

CL=5 pF

ST = High,

CL=10 pF

2.4

1.9

ns

1 pixel/clock, PIXS = low, OCK_INV = low

1.8

tsu1

Setup time, data and control signal to

falling edge of ODCK

2 pixel/clock, PIXS = high, STAG/ = high,

OCK_INV = low

3.8

ns

falling edge of ODCK

2 pixel and STAG, PIXS = high,

STAG/ = low, OCK_INV = low

0.7

1 pixel/clock, PIXS = low, OCK_INV = low

0.6

th1

Hold time, data and control signal to

falling edge of ODCK

2 pixel and STAG, PIXS = high,

STAG/ = low, OCK_INV = low

2.5

ns

falling edge of ODCK

2 pixel/clock, PIXS = high,

STAG/ = high, OCK_INV = low

2.9

1 pixel/clock, PIXS = low, OCK_INV = high

2.1

tsu2

Setup time, data and control signal to

rising edge of ODCK

2 pixel/clock, PIXS = high,

STAG/ = high, OCK_INV = high

4

ns

rising edge of ODCK

2 pixel and STAG, PIXS = high,

STAG/ = low, OCK_INV = high

1.5

1 pixel/clock, PIXS = low, OCK_INV = high

0.5

th2

Hold time, data and control signal to

rising edge of ODCK

2 pixel and STAG, PIXS = high,

STAG/ = low, OCK_INV = high

2.4

ns

rising edge of ODCK

2 pixel/clock, PIXS = high,

STAG/ = high, OCK_INV = high

2.1

fODCK

ODCK frequency

PIX = Low (1-PIX/CLK)

25

165

MHz

fODCK

ODCK frequency

PIX = High (2-PIX/CLK)

12.5

82.5

MHz

ODCK duty-cycle

45%

60%

75%

† Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection.

‡ tbit is 1/10 the pixel time, tpix

§ tpix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpix in 1-pixel/clock mode or 2tpix when in

2-pixel/clock mode.

¶ Measured differentially at 50% crossing using ODCK output clock as trigger.

# Rise and fall times measured as time between 20% and 80% of signal amplitude.

|| Data and control signals are : QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[3:1]

NOTE 6: By characterization