TMS416400, TMS416400P, TMS417400, TMS417400P

TMS426400, TMS426400P, TMS427400, TMS427400P

4194304-WORD BY 4-BIT HIGH-SPEED DRAMS

SMKS881B – MAY 1995 – REVISED AUGUST 1995

16

POST OFFICE BOX 1443

RAS

CAS

Address

W

OE

DQ1 – DQ4

tRC

Row

Column

Don’t Care

Don’t Care

Don’t Care

Don’t Care

Don’t Care

Valid Data Out

tRAS

tRP

tCSH

tT

tRCD

tRSH

tCRP

tCAS

tRAD

tASC

tRAL

tASR

tRCS

tCAH

tRRH

tRCH

tCAC

tOFF

tAA

tCLZ

tRAC

tOEA

tROH

tOEZ

tCP

See Note A

Hi-Z

tRAH

tCAL

tOH

tOHO

NOTE A: Output can go from high-impedance state to an invalid-data state prior to the specified access time.

Figure 3. Read-Cycle Timing