TMS416400, TMS416400P, TMS417400, TMS417400P

TMS426400, TMS426400P, TMS427400, TMS427400P

4194304-WORD BY 4-BIT HIGH-SPEED DRAMS

SMKS881B – MAY 1995 – REVISED AUGUST 1995

19

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

RAS

CAS

Address

W

OE

DQ1 – DQ4

tRWC

Row

Column

Don’t Care

Don’t Care

Don’t Care

Data

Out

Don’t Care

Don’t Care

Data

In

tRAS

tRCD

tT

tCAS

tRP

tCRP

tCP

tT

tCAH

tASC

tRAH

tASR

tRAD

tRCS

tRWD

tRWL

tWP

tAWD

tCWD

tCAC

tDS

tDH

tAA

tCLZ

tRAC

tOEA

tOEZ

tOED

tOEH

See Note A

tCWL

tOHO

NOTE A: Output can go from high-impedance state to an invalid-data state prior to the specified access time.

Figure 6. Read-Write-Cycle Timing