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ADP3522

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Printed Circuit Board Layout Considerations

Use the following general guidelines when designing printed

circuit boards:

1. Connect the battery to the VBAT, VBAT2, and VRTCIN

pins of the ADP3522. Locate the input capacitor as close to

the pins as possible.

2. VAN and VTCXO output capacitors should be returned to

AGND.

3. VCORE, VMEM, and VSIM output capacitors should be

returned to DGND.

4. Split the ground connections. Use separate traces or planes

for the analog, digital, and power grounds and tie them to-

gether at a single point, preferably close to the battery return.

5. Run a separate trace from the BATSNS pin to the battery to

prevent voltage drop error in the MVBAT measurement.

6. Kelvin connect the charger’s sense resistor by running

separate traces to the CHRIN pin and ISENSE pin. Make

sure the traces are terminated as close to the resistor’s

body as possible.

7. Use the best industry practice for thermal considerations

during the layout of the ADP3522 and charger components.

Careful use of copper area, weight, and multilayer construc-

tion all contribute to improved thermal performance.

LFCSP Layout Considerations

The CSP package has an exposed die paddle on the bottom that

efficiently conducts heat to the PCB. In order to achieve the

optimum performance from the CSP package, special consider-

ation must be given to the layout of the PCB. Use the following

layout guidelines for the CSP package:

1. The pad pattern is given in Figure 11. The pad dimension

should be followed closely for reliable solder joints while

maintaining reasonable clearances to prevent solder bridging.

2. The thermal pad of the CSP package provides a low thermal

impedance path (approximately 15

°C/W) to the PCB.

Therefore, the PCB must be properly designed to effectively

conduct the heat away from the package. This is achieved by

adding thermal vias to the PCB, which provide a thermal

path to the inner or bottom layers. See Figure 12 for the

recommended via pattern. Note that the via diameter is

small. This is to prevent the solder from flowing through the

via and leaving voids in the thermal pad solder joint.

Note that the thermal pad is attached to the die substrate;

the thermal planes that the vias attach the package to must

be electrically isolated or connected to VBAT. Do NOT

connect the thermal pad to ground.

3. The solder mask opening should be about 120 microns (4.7 mils)

larger than the pad size resulting in a minimum 60 microns

(2.4 mils) clearance between the pad and the solder mask.

4. The paste mask opening is typically designed to match the

pad size used on the peripheral pads of the LFCSP package.

This should provide a reliable solder joint as long as the

stencil thickness is about 0.125 mm.

The paste mask for the thermal pad needs to be designed for

the maximum coverage to effectively remove the heat from

the package. However, due to the presence of thermal vias

and the large size of the thermal pad, eliminating voids may

not be possible. Also, if the solder paste coverage is too large,

solder joint defects may occur. Therefore, it is recommended

to use multiple small openings over a single big opening in

designing the paste mask. The recommended paste mask

pattern is given in Figure 13. This pattern will result in about

80% coverage, which should not degrade the thermal perfor-

mance of the package significantly.

5. The recommended paste mask stencil thickness is 0.125 mm.

A laser cut stainless steel stencil with trapezoidal walls should

be used.

A “No Clean,” Type 3 solder paste should be used for

mounting the LFCSP package. Also, a nitrogen purge during

the reflow process is recommended.

6. The package manufacturer recommends that the reflow

temperature should not exceed 220

°C and the time above

liquids is less than 75 seconds. The preheat ramp should be

°C/second or lower. The actual temperature profile depends

on the board’s density and must be determined by the assembly

house as to what works best.

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