RT1710 datasheet(13/14 Pages) RICHTEK

13 / 14 page

RT1710

DS1710-00 May 2016

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Figure 3. Derating Curve of Maximum Power Dissipation

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TAis

the ambient temperature, and

θJAis the junction to ambient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance,

θJA, is layout dependent. For

WDFN-8L 2x3 package, the thermal resistance,

θJA, is

31.5

°C/W on a standard JEDEC 51-7 four-layer thermal

test board. The maximum power dissipation at TA = 25

°C

can be calculated by the following formula :

PD(MAX) = (125

°C − 25°C) / (31.5°C/W) = 3.17W for

WDFN-8L 2x3 package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance,

θJA. The derating curve in Figure 3 allows the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

100

125

Ambient Temperature (°C)

Four-Layer PCB

Layout Consideration



PCB layout is very important for designing e-marked IC

(RT1710) circuits.



The VCON1 and VCON2 traces should be wide (10mil)

and short especially for the current loop.



Connect VCON1/VCON2 pins with bypass capacitor,

and as near the pins as possible.



The exposed pad of the chip should be connected to a

large ground plane for thermal consideration.



Keep the CC1 traces away from those sensing pins

(D+, D-, SSTX+, SSTX-, SSRX+, SSRX-, SBU).

Figure 4. PCB Layout Guide

The exposed pad of the chip should be

connected to a large ground plane for

thermal consideration.

CC PIN

VCONN

0.1µF

RT1710

SDA

SCL

GND

VCON2

VCON1

CCIN

Test pad

VCONN

(Another side)

0.1µF

Keep the CC1 traces away from those sensing pins

(D+,D-,SSTX+,SSTX-,SSRX+,SSRX-,SBU)

The VCON1 and VCON2

traces should be wide (10mil)

and short especially for the

current loop.

Connect VCON1/VCON2 pins

with bypass capacitor,and as

near the pins as possible.

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