P87LPC760 datasheet(44/56 Pages) PHILIPS

44 / 56 page

Philips Semiconductors

Preliminary data

P87LPC760

Low power, low price, low pin count (14 pin)

microcontroller with 1 kbyte OTP

2002 Mar 07

instructions that can be executed before the watchdog overflows

may be quite small.

Watchdog Reset

If a watchdog reset occurs, the internal reset is active for

approximately one microsecond. If the CPU clock was still running,

code execution will begin immediately after that. If the processor

was in Power Down mode, the watchdog reset will start the

oscillator and code execution will resume after the oscillator is

stable.

SU01633

WATCHDOG

INTERRUPT

20-BIT COUNTER

STATE CLOCK

WDTE (UCFG1.7)

BOF (PCON.5)

POF (PCON.4)

WATCHDOG

RESET

CLEAR

8 MSBs

8 TO 1 MUX

WATCHDOG

FEED DETECT

WDOVF

(WDCON.5)

WDS2–0

(WDCON.2–0)

WDTE + WDRUN

WDCLK * WDTE

500 kHz

RC OSCILLATOR

ENABLE

CLOCK OUT

Figure 36. Block Diagram of the Watchdog Timer

BIT

SYMBOL

FUNCTION

WDCON.7, 6

—

Reserved for future use. Should not be set to 1 by user programs.

WDCON.5

WDOVF

Watchdog timer overflow flag. Set when a watchdog reset or timer overflow occurs. Cleared when

the watchdog is fed.

WDCON.4

WDRUN

Watchdog run control. The watchdog timer is started when WDRUN = 1 and stopped when

WDRUN = 0. This bit is forced to 1 (watchdog running) if the WDTE configuration bit = 1.

WDCON.3

WDCLK

Watchdog clock select. The watchdog timer is clocked by CPU clock/6 when WDCLK = 1 and by

the watchdog RC oscillator when WDCLK = 0. This bit is forced to 0 (using the watchdog RC

oscillator) if the WDTE configuration bit = 1.

WDCON.2–0 WDS2–0

Watchdog rate select.

WDS2–0

Timeout Clocks

Minimum Time

Nominal Time

Maximum Time

0 0 0

8,192

10 ms

16 ms

23 ms

0 0 1

16,384

20 ms

32 ms

45 ms

0 1 0

32,768

41 ms

65 ms

90 ms

0 1 1

65,536

82 ms

131 ms

180 ms

1 0 0

131,072

165 ms

262 ms

360 ms

1 0 1

262,144

330 ms

524 ms

719 ms

1 1 0

524,288

660 ms

1.05 sec

1.44 sec

1 1 1

1,048,576

1.3 sec

2.1 sec

2.9 sec

WDS0

SU01634

WDS1

WDS2

WDCLK

WDRUN

WDOVF

—

WDCON

Reset Value:

S 30h for a watchdog reset.

S 10h for other rest sources if the watchdog is enabled via the WDTE configuration bit.

S 00h for other reset sources if the watchdog is disabled via the WDTE configuration bit.

Not Bit Addressable

Address: A7h

Figure 37. Watchdog Timer Control Register (WDCON)

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