SC16C550 datasheet(13/52 Pages) PHILIPS

13 / 52 page

Philips Semiconductors

SC16C550

UART with 16-byte FIFO and IrDA encoder/decoder

Product data

Rev. 05 — 19 June 2003

13 of 52

9397 750 11619

6.4 Software ﬂow control

When software ﬂow control is enabled, the SC16C550 compares one or two

sequential receive data characters with the programmed Xon or Xoff character

value(s). If receive character(s) (RX) match the programmed values, the SC16C550

will halt transmission (TX) as soon as the current character(s) has completed

transmission. When a match occurs, the receive ready (if enabled via Xoff IER[5])

ﬂags will be set and the interrupt output pin (if receive interrupt is enabled) will be

activated. Following a suspension due to a match of the Xoff characters’ values, the

SC16C550 will monitor the receive data stream for a match to the Xon1,2 character

value(s). If a match is found, the SC16C550 will resume operation and clear the ﬂags

(ISR[4]).

Reset initially sets the contents of the Xon/Xoff 8-bit ﬂow control registers to a logic 0.

Following reset, the user can write any Xon/Xoff value desired for software ﬂow

control. Different conditions can be set to detect Xon/Xoff characters and

suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,

the SC16C550 compares two consecutive receive characters with two software ﬂow

control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions

accordingly. Under the above described ﬂow control mechanisms, ﬂow control

characters are not placed (stacked) in the user accessible RX data buffer or FIFO.

When using a software ﬂow control the Xon/Xoff characters cannot be used for data

transfer.

In the event that the receive buffer is overﬁlling and ﬂow control needs to be executed,

the SC16C550 automatically sends an Xoff message (when enabled) via the serial

TX output to the remote modem. The SC16C550 sends the Xoff1,2 characters as

soon as received data passes the programmed trigger level. To clear this condition,

the SC16C550 will transmit the programmed Xon1,2 characters as soon as receive

data drops below the programmed trigger level.

(1) RTS is de-asserted when the receiver receives the ﬁrst data bit of the sixteenth byte. The receive FIFO is full after ﬁnishing

the sixteenth byte.

(2) RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing, or there is

more than one byte of space available.

(3) When the receive FIFO is full, the ﬁrst receive buffer register read re-asserts RTS.

Fig 8.

RTS functional timing waveforms, RCV FIFO trigger level = 14 bytes.

BYTE 14

BYTE 15

RTS

IOR

(RD RBR)

START

BYTE 18

STOP

START

BYTE 16

STOP

RTS RELEASED AFTER THE

FIRST DATA BIT OF BYTE 16

002aaa051

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