MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2

Freescale Semiconductor

5

General Parameters

4.3.1

Clock AC Specifications

Figure 7 through Figure 10 show the DLL locking range loop delay vs. frequency of operation for 29 angstrom parts

(400 and 466 MHz). These graphs define the areas of DLL locking for various modes. The gray areas show where

the DLL will lock.

Register settings that define each DLL mode are shown in Table 9.

The DLL_MAX_DELAY bit can lengthen the amount of time through the delay line. This is accomplished by

increasing the time between each of the 128 tap points in the delay line. Although this increased time makes it easier

to guarantee that the reference clock will be within the DLL lock range, it also means there may be slightly more

jitter in the output clock of the DLL, should the phase comparator shift the clock between adjacent tap points. Refer

to Freescale application note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines, for details on

memory design.

Table 9. DLL Mode Definition

DLL Mode

Value of Bit 2 of Config

Register at 0x76

Value of Bit 7 of Config

Register at 0x72

Normal tap delay,

No DLL extend

00

Normal tap delay,

DLL extend

01

Max tap delay,

No DLL extend

10

Max tap delay,

DLL extend

11