MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2

Freescale Semiconductor

11

PLL Configuration

6

PLL Configuration

The MPC8245 internal PLLs are configured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN (PCI bus)

frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO) frequency of

operation for the PCI-to-memory frequency multiplying and the MPC603e CPU PLL (VCO) frequency of operation

for memory-to-CPU frequency multiplying. The PLL configurations for the 400- and 466-MHz parts are shown in

Table 18 and Table 19, respectively.

Table 18. PLL Configurations for the 400-MHz Part Offering

Ref

PLL_CFG

Multipliers

PCI Clock Input

(PCI_SYNC_IN)

(MHz)

Periph

Logic/Mem

Bus Clock

Range

(MHz)

CPU Clock

Range

(MHz)

PCI-to-Mem

(Mem VCO)

Mem-to-CPU

(CPU VCO)

0

00000

75–132

188–330

3 (2)

2.5 (2)

1

00001

75–132

225–396

3 (2)

3 (2)

2

50–66

225–297

1 (4)

4.5 (2)

3

50–66

100–133

1 (Bypass)

2 (4)

4

00100

50–92

100–184

2 (4)

2 (4)

6

Bypass

Bypass

Bypass

7 (Rev. B)

00111

60–66

180–198

1 (Bypass)

3 (2)

7 (Rev. D)

100–112

350–392

4 (2)

3.5 (2)

8

01000

60–66

180–198

1 (4)

3 (2)

9

01001

90–132

180–264

2 (2)

2 (2)

A

01010

50–88

225–396

2 (4)

4.5 (2)

B

01011

68–99

204–297

1.5 (2)

3 (2)

C

01100

72–92

180–230

2 (4)

2.5 (2)

D

01101

68–99

238–347

1.5 (2)

3.5 (2)

E

01110

60–92

180–276

2 (4)

3 (2)

F

01111

75–114

263–399

3 (2)

3.5 (2)

10

10000

60–132

180–264

3 (2)

2 (2)

11

10001

100–132

250–330

4 (2)

2.5 (2)

12

10010

90–99

180–198

1.5 (2)

2 (2)

13

10011

100–132

300–396

4 (2)

3 (2)

14

10100

52–94

182–329

2 (4)

3.5 (2)

15

10101

68–100

272–400

2.5 (2)

4 (2)

16

10110

50–92

200–368

2 (4)

4 (2)

17

10111

100–132

200–264

4 (2)

2 (2)