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ML610Q419C Datasheet(PDF) 31 Page - LAPIS Semiconductor Co., Ltd. |
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ML610Q419C Datasheet(HTML) 31 Page - LAPIS Semiconductor Co., Ltd. |
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31 / 38 page ![]() FEDL610Q419-07 ML610Q419/ML610Q419C 31/38 AC CHARACTERISTICS (Synchronous Serial Port) (VDD = 1.3 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C, unless otherwise specified) Parameter Symbol Condition Rating Unit Min. Typ. Max. SCLKn input cycle (slave mode) tSCYC When high-speed oscillation is not active* 2 (V DD = 1.3 to 3.6V) 10 µs When high-speed oscillation is active* 3 (V DD = 1.8 to 3.6V) 1 µs SCLKn output cycle (master mode) tSCYC SCLKn* 1 s SCLKn input pulse width (slave mode) tSW When high-speed oscillation is not active* 2 (V DD = 1.3 to 3.6V) 4 µs When high-speed oscillation is active* 3 (V DD = 1.8 to 3.6V) 0.4 µs SCLKn output pulse width (master mode) tSW SCLKn* 1 ×0.4 SCLKn* 1 ×0.5 SCLKn* 1 ×0.6 s SOUTn output delay time (slave mode) tSD When high-speed oscillation is not active* 2 (V DD = 1.3 to 3.6V) 500 ns When high-speed oscillation is active* 3 (V DD = 1.8 to 3.6V) 240 SOUTn output delay time (master mode) tSD When high-speed oscillation is not active* 2 (V DD = 1.3 to 3.6V) 500 ns When high-speed oscillation is active* 3 (V DD = 1.8 to 3.6V) 240 SINn input setup time (slave mode) tSS 80 ns SINn input setup time (master mode) tSS When high-speed oscillation is not active* 2 (V DD = 1.3 to 3.6V) 500 ns When high-speed oscillation is active* 3 (V DD = 1.8 to 3.6V) 240 SINn input hold time tSH When high-speed oscillation is not active* 2 (V DD = 1.3 to 3.6V) 300 ns When high-speed oscillation is active* 3 (V DD = 1.8 to 3.6V) 80 n= 0,1 *1: Clock period selected with SnCK3–0 of the serial port n mode register (SIOnMOD1) * 2: When RC oscillation is selected with OSCM1–0 of the frequency control register (FCON0) * 3: When Crystal/ceramic oscillation, built-in PLL oscillation, or external clock input is selected with OSCM1–0 of the frequency control register (FCON0) tSD SCLKn* SINn* SOUTn* *: Indicates the secondary function of the port. tSD tSS tSH tSW tSW tSCYC |
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