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exar.com/CLC1200

Rev 2E

CLC1200

Grounding

The output voltage of the CLC1200 is developed with

respect to the potential on the reference terminal (pin 8).

Simply tie the REF pin to the appropriate “local ground” to

resolve many grounding problems.

To isolate low level analog signals from a noisy digital

environment, many data acquisition components have

separate analog and digital ground pins. Use separate

ground lines (analog and digital) to minimize current flow

from sensitive areas to system ground. These ground

returns must be tied together at some point, usually best at

the ADC.

Layout Considerations

General layout and supply bypassing play major roles in

high frequency performance. Exar has evaluation boards to

use as a guide for high frequency layout and as an aid in

device testing and characterization. Follow the steps below

as a basis for high frequency layout:

■

■

Include 6.8µF and 0.1µF ceramic capacitors for power supply

decoupling

■

■

Place the 6.8µF capacitor within 0.75 inches of the power pin

■

■

Place the 0.1µF capacitor within 0.1 inches of the power pin

■

■

Remove the ground plane under and around the part,

especially near the input and output pins to reduce parasitic

capacitance

■

■

Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts below for more

information.

Evaluation Board Information

The following evaluation boards are available to aid in the

testing and layout of these devices:

Evaluation Board #

Products

CEB024

CLC1200 in SOIC-8

Evaluation Board Schematics

Evaluation board schematics and layouts are shown in

Figures 6-8. These evaluation boards are built for dual-

supply operation. Follow these steps to use the board in a

single-supply application:

directly connected to the ground plane.

Figure 6. CEB024 Schematic

Figure 7. CEB024 Top View

Figure 8. CEB024 Bottom View