LM5642 datasheet(16/24 Pages) NSC

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Operating Descriptions (Continued)

The peak current limit is set by an external resistor con-

nected between the ILIMx pin and the KSx pin. An internal

10µA current sink on the ILIMx pin produces a voltage

across the resistor to set the current limit threshold which is

compared to the current sense voltage. A 10nF capacitor

across this resistor is required to filter unwanted noise that

could improperly trip the current limit comparator.

Current limit is activated when the inductor current is high

enough to cause the voltage at the RSNSx pin to be lower

than that of the ILIMx pin. This toggles the comparator, thus

turning off the top FET immediately. The comparator is dis-

abled either when the top FET is turned off or during the

leading edge blanking time. The equation for current limit

resistor, R

lim, is as follows:

(4)

Where Ilim is the load current at which the current limit

comparator will be tripped.

When sensing current across the top FET, replace Rsns with

the R

DS-ON of the FET. This calculated Rlim value guaran-

tees that the minimum current limit will not be less than Imax.

It is recommended that a 1% tolerance resistor be used.

When sensing across the top FET, R

DS-ON will show more

variation than a current sense resistor, largely due to tem-

perature. R

DS-ON will increase proportional to temperature

according to a specific temperature coefficient. Refer to the

manufacturer’s datasheet to determine the range of R

DS-ON

values over operating temperature or see the Component

Selection section (Equation 4) for a calculation of maximum

DS-ON. This will prevent RDS-ON variations from prematurely

setting off the current limit comparator as the operating

temperature increases.

To ensure accurate current sensing using V

DS sense, special

attention in board layout is required. The KSx and RSNSx

pins require separate traces to form a Kelvin connection to

the corresponding current sense nodes. In addition, the filter

components R14, R16, C14, C15 should be removed.

INPUT UNDER VOLTAGE LOCKOUT (UVLO)

The input under-voltage lock out threshold, which is sensed

via the VLIN5 internal LDO output, is 4.0V (typical). Below

this threshold, both HDRVx and LDRVx will be turned off and

the internal 480

Ω MOSFETs will be turned on to discharge

the output capacitors through the SWx pins. During UVLO,

the ON/SS pins will sink 5mA to discharge the soft start

capacitors and turn off both channels. As the input voltage

increases again above 4.0V, UVLO will be de-activated, and

the device will restart again from soft start phase. If the

voltage at VLIN5 remains below 4.5V, but above the 4.0V

UVLO threshold, the device cannot be guaranteed to oper-

ate within specification.

If the input voltage is between 4.0V and 5.2V, the VLIN5 pin

will not regulate, but will follow approximately 200mV below

the input voltage.

DUAL-PHASE PARALLEL OPERATION

In applications with high output current demand, the two

switching channels can be configured to operate as a two

phase converter to provide a single output voltage with

current sharing between the two switching channels. This

approach greatly reduces the stress and heat on the output

stage components while lowering input ripple current. The

sum of inductor ripple current is also reduced which results

in lowering output ripple voltage. Figure 2 shows an example

of a typical two-phase circuit. Because precision current

sense is the primary design criteria to ensure accurate cur-

rent sharing between the two channels, both channels must

use external sense resistors for current sensing. To minimize

the error between the error amplifiers of the two channels, tie

the feedback pins FB1 and FB2 together and connect to a

single voltage divider for output voltage sensing. Also, tie the

COMP1 and COMP2 together and connect to the compen-

sation network. ON/SS1 and ON/SS2 must be tied together

to enable and disable both channels simultaneously.

EXTERNAL FREQUENCY SYNC

The LM5642 has the ability to synchronize to external

sources in order to set the switching frequency. This allows

the chip to use frequencies from 150kHz to 250kHz. Lower-

ing the switching frequency allows a smaller minimum duty

cycle, DMIN, and hence a greater range between input and

output voltage. Increasing switching frequency allows the

use of smaller output inductors and output capacitors (See

Component Selection). In general, synching all the switching

frequencies in multi-converter systems makes filtering of the

switching noise easier.

The sync input can be from a system clock, from another

switching converter in the system, or from any other periodic

signal with a low-level less than 1.4V and a high level greater

than 2V. Both CMOS and TTL level inputs are acceptable.

The LM5642 uses a fixed delay scheme in order to ensure a

180˚ phase difference between Channel 1 and Channel 2.

Due the nominal switching frequency of 200kHz, which cor-

responds to a switching period of 5µs, Channel 2 always

begins its period 2.5µs after Channel 1 (Figure 8a). When

the converter is synched to a frequency other than 200kHz,

the switching period is reduced or increased, while the fixed

delay between Channel 1 and Channel 2 remains the same.

The phase difference between channels is therefore no

longer 180˚. At the extremes of the sync range, the phase

difference drops to 135˚ (Figure 8b) and Figure 8c). The

result of this lower phase difference is a reduction in the

maximum duty cycle of one channel that will not overlap the

duty cycle of the other. As shown in Input Capacitor Selec-

20060110

FIGURE 7. Current Sense and Current Limit

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