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CS61535A Datasheet(PDF) 6 Page - Cirrus Logic

Part # CS61535A
Description  T1/E1 LINE INTERFACE
PDF  48 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS61535A Datasheet(HTML) 6 Page - Cirrus Logic

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T1 SWITCHING CHARACTERISTICS (TA = -40
°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol
Min
Typ
Max
Units
Crystal Frequency
(Note 29)
fc
-
6.176000
-
MHz
ACLKI Duty Cycle
tpwh3/tpw3
40
-
60
%
ACLKI Frequency
(Note 30)
faclki
-1.544
-
MHz
RCLK Duty Cycle
(Notes 31, 32)
tpwh1/tpw1
-
-
78
29
-
-
%
%
RCLK Cycle Width
(Note 32)
tpw1
tpwh1
tpwl1
320
130
100
648
190
458
980
240
850
ns
ns
ns
Rise Time, All Digital Outputs
(Note 33)
tr
-
-
85
ns
Fall Time, All Digital Outputs
(Note 33)
tf
-
-
85
ns
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2
25
-
-
ns
RPOS/RNEG Valid Before RCLK Falling
(Note 34)
tsu1
150
274
-
ns
RDATA Valid Before RCLK Falling
(Note 35)
tsu1
150
274
-
ns
RPOS/RNEG Valid Before RCLK Rising
(Note 31)
tsu1
150
274
-
ns
RPOS/RNEG Valid After RCLK Falling
(Note 34)
th1
150
274
-
ns
RDATA Valid After RCLK Falling
(Note 35)
th1
150
274
-
ns
RPOS/RNEG Valid After RCLK Rising
(Note 31)
th1
150
274
-
ns
TCLK Frequency
ftclk
-1.544
-
MHz
TCLK Pulse Width
(Notes 12, 31, 34, 36, 37)
(Notes 35, 36, 37)
tpwh2
80
150
-
-
500
500
ns
ns
Notes: 29. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.
30. ACLKI provided by an external source or TCLK, but
not RCLK.
31. Hardware Mode, or Host Mode (CLKE = 0).
32. RCLK cycle width will vary with extent by which pulses displaced by jitter. Specified under worst case
jitter conditions: 0.4 UI AMI data displacement for T1 and 0.2 UI AMI data displacement for E1.
33. At max load of 1.6 mA and 50 pF.
34. Host Mode (CLKE = 1).
35. Extended Hardware Mode.
36. The maximum TCLK burst rate is 5 MHz and tpw2(min) = 200 ns. The maximum gap size that can
be tolerated on TCLK is 12 VI.
37. The transmitted pulse width does not depend on the TCLK duty cycle.
RCLK
tpw1
tpwl1
tpwh1
HOST MODE
(CLKE = 1)
EXTENDED
HARDWARE
MODE OR
HARDWARE
HOST MODE
(CLKE = 0)
MODE OR
RCLK
RPOS
RNEG
su1
h1
tt
RDATA
BPV
Figure 1. Recovered Clock and Data Switching Characteristics
CS61535A
6
DS40F2



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