CS61535A datasheet(31/48 Pages) CIRRUS

31 / 48 page

Semiconductor be used for T1 applications, and

that the CXT8192 be used for E1 applications.

Interfacing The CS61535A With the CS62180B

T1 Transceiver

To interface with the CS62180B, connect the de-

vices as shown in Figure A4. In this case, the

CS61535A and CS62180B are in Host Mode con-

trolled by a microprocessor serial interface. If the

CS61535A is used in Hardware Mode, then the

CS61535A RCLK output must be inverted before

being input to the CS62180B. If the CS61535A is

used in Extended Hardware Mode, the CS61535A

RCLK output does not need to be inverted before

being input to the CS62180B.

CS61534 Compatibility

The CS61535A is pin compatible with the

CS61534. The CS61535A has greater jitter toler-

ance for both transmitter and receiver, and it

provides more jitter attenuation starting at jitter

frequencies of 6 Hz. The greater jitter tolerance

and attenuation in the transmit path makes the

CS61535A more suitable for CCITT demultiplex-

ing applications where eight bits can be dropped

from the clock/data stream at once. Similarly,

these parts can be used in SONET applications

with the addition of some external circuitry.

The main differences of the CS61535A relative

to the CS61534 is:

1) On the CS61535A, selection of LEN 2/1/0 =

0/0/0 changes the voltage at which the receiver

accepts an input as a pulse (slicing level) from

65% to 50% of the peak pulse amplitude. Lower-

ing the data slicing level will improve receiver

sensitivity at long cable lengths when the data is

jittered. A 50% slicing level will also improve

crosstalk sensitivity for channels where received

pulses do not have undershoot.

2) There are differences in the functionality of the

ACLKI (ACLK) input on the CS61534 and

CS61535A. ACKLI (ACLK) is used as the trans-

mit clock in the transmit all ones (TAOS) mode.

On the CS61535A, ACLKI is used as a calibra-

tion reference for the receiver clock recovery

circuit and therefore may not be supplied by

RCLK. On the CS61534, ACLK may be supplied

by RCLK . If an external clock is not provide on

the ACLKI input of the CS61535A, the crystal

oscillator is used to calibrate the receiver clock

recovery circuit.

3) On the CS61535A, the Host Mode status regis-

ter bits 5, 6 and 7 are encoded so that state

changes on LOS and DPM may be reported.

4) RCLK on the CS61534 has a 50% duty cycle,

while RCLK on the CS61535A has a duty cycle

which is typically 30% or 70%. Also, the

CS61535A RCLK duty cycle and instantaneous

frequency vary with received jitter and may ex-

hibit 1/13 UIpp quantization jitter even when the

incoming signal is jitter free.

5) The CS61535A requires 25 ns of setup time on

TPOS and TNEG before the falling edge of

TCLK and 25 ns of hold time on these inputs af-

ACLKI

TCLK

RGND

RCLK

RV+

+5V

0.1uF

RPOS

RNEG

TPOS

TNEG

CS62180B

MODE

V+

CLKE

SCLK

SDO

SDI

TCLK

TPOS

TNEG

RNEG

RPOS

RCLK

SCLK

SDO

SDI

TO HOST CONTROLLER

V+

100k

1.544 MHz

CLOCK

CS61535A

V+

22k

SIGNAL

68uF

INT

Figure A4. Interfacing the CS61535A with the

CS62180B (Host Mode)

CS61535A

DS40F2

CS61535A Datasheet(PDF) 31 Page - Cirrus Logic

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